ZL50052GAC ZARLINK [Zarlink Semiconductor Inc], ZL50052GAC Datasheet - Page 23

• Manufacturer Part Number: ZL50052GAC
• Description: 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read exceeds 2 frames.
Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read is less than 2 frames.
6.0
The 8 K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 4,096 locations. See Table 5, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA handshake when accessed, but any data read from the bus will be invalid.
7.0
7.1
The recommended power-up sequence is for the V
power-up of the V
powered-up simultaneously, but neither should 'lead' the V
All supplies may be powered-down simultaneously.
Serial Output Data
Serial Output Data
Serial Input Data
Serial Input Data
Power-Up Sequence
Microprocessor Port
Device Power-Up, Initialization and Reset
Frame
Frame
Figure 12 - Data Throughput Delay with Input Ch0 Switched to Output Ch13
Figure 13 - Data Throughput Delay with Input Ch13 Switched to Output Ch0
DD_PLL
and V
Frame N-2 Data
Frame N-2 Data
Frame N
Frame N
Frame N Data
Frame N Data
DD_CORE
Frame N+1Data
Frame N-1 Data
Frame N+1Data
Frame N-1 Data
Frame N+1
Frame N+1
supplies (nominally +1.8 V). The V
2 Frames + (n - m)
2 Frames + (n - m)
Zarlink Semiconductor Inc.
Frame N+2 Data
Frame N+2 Data
ZL50052
Frame N+2
Frame N+2
Frame N Data
Frame N Data
DD_IO
23
DD_IO
supply (nominally +3.3 V) to be established before the
Frame N+3 Data
Frame N+1 Data
Frame N+3 Data
Frame N+1 Data
Frame N+3
Frame N+3
supply by more than 0.3 V.
Frame N+4 Data
Frame N+2 Data
Frame N+4 Data
Frame N+2 Data
Frame N+4
Frame N+4
DD_PLL
and V
Frame N+5 Data
Frame N+3 Data
Frame N+5 Data
Frame N+3 Data
Frame N+5
Frame N+5
DD_CORE
supplies may be
Data Sheet