ZL50110_08 ZARLINK [Zarlink Semiconductor Inc], ZL50110_08 Datasheet

ZL50110_08

Manufacturer Part Number

ZL50110_08

Description

128, 256, 512 and 1024 Channel CESoP Processors

Manufacturer

ZARLINK [Zarlink Semiconductor Inc]

Datasheet

1.ZL50110_08.pdf (112 pages)

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Features

General

•

Circuit Emulation Services

•

TDM Interfaces

•

Circuit Emulation Services over Packet (CESoP)

transport for MPLS, IP and Ethernet networks

On chip timing & synchronization recovery across

a packet network

Grooming capability for Nx64 Kbps trunking

Supports ITU-T Recommendation Y.1413 and

Y.1453

Supports IETF RFC4553 and RFC5086

Supports MEF8 and MFA 8.0.0

Structured, synchronous CESoP with clock

recovery

Unstructured, asynchronous CESoP, with integral

per stream clock recovery

Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports

H.110, H-MVIP, ST-BUS backplanes

Up to 1024 bi-directional 64 Kbps channels

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

(L IU , F ra m e r, B a c kp la n e )

S tra tu m 3 D P L L

D u a l R e fe re n ce

(J itte r B u ffe r C o m p e n s a tio n fo r 1 6 -1 2 8 m s o f P a c k e t D e la y V a ria tio n )

P e r P o rt D C O fo r

C lo c k R e c o v e ry

In te rfa c e

T D M

Figure 1 - ZL50111 High Level Overview

O n C h ip P a c k e t M e m o ry

Zarlink Semiconductor Inc.

3 2 -b it M o to ro la c o m p a tib le

D M A fo r s ig n a lin g p a c k e ts

M u lti-P ro to c o l

IP v4 , IP v6 , M P L S ,

E C ID , V L A N , U s e r

H o st P ro ce ss o r

P W , R T P , U D P ,

D e fin e d , O th e rs

P ro c e s s in g

In te rfa ce

E n g in e

P a c k e t

128, 256, 512 and 1024 Channel CESoP

•

Network Interfaces

•

System Interfaces

•

ZL50110GAG

ZL50111GAG

ZL50112GAG

ZL50114GAG

ZL50110GAG2 552 PBGA** Trays, Bake & Drypack

ZL50111GAG2

ZL50112GAG2 552 PBGA** Trays, Bake & Drypack

ZL50114GAG2 552 PBGA** Trays, Bake & Drypack

Direct connection to LIUs, framers, backplanes

Dual reference Stratum 4 and 4E DPLL for

synchronous operation

Up to 3 x 100 Mbps MII Fast Ethernet or Dual

Redundant 1000 Mbps GMII/TBI Ethernet

Interfaces

Flexible 32 bit host CPU interface (Motorola

PowerQUICC

On-chip packet memory for self-contained

operation, with buffer depths of over 16 ms

Up to 8 Mbytes of off-chip packet memory,

supporting buffer depths of over 128 ms

In te rfa c e (o p tio n a l)

E x te rn a l M e m o ry

**Pb Fee Tin Silver/Copper

Ordering Information

(M II, G M II, T B I)

(0 - 8 M b y te s )

™

In te rfa c e

Z B T -S R A M

552 PBGA

552 PBGA** Trays, Bake & Drypack

P a c k e t

T rip le

-40°C to +85°C

M A C

compatible)

ZL50110/11/12/14

Trays, Bake & Drypack

Processors

Data Sheet

April 2008

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