ZL50110_08 ZARLINK [Zarlink Semiconductor Inc], ZL50110_08 Datasheet - Page 11

• Manufacturer Part Number: ZL50110_08
• Description: 128, 256, 512 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

1.0
The following table captures the changes from the April 2007 issue.
The following table captures the changes from the February 2006 issue.
1, 4, 23, 51
1, 2 and 3
75 and 77
1, 58, 74,
Several
and 58
Page
Page
13
32
48
55
56
58
60
62
63
64
64
65
72
86
93
94
97
95
Changes Summary
Include ZL50112 device
Standard
Stratum 3 DPLL
STS-1 stream
Section 2.0
Section 3.3
Section 3.7.2
Section 4.6
Section 5.0
Section 5.3
Section 5.4
Section 5.4.2
Section 5.8
Section 6.0
Section 6.1
Section 6.2
Section 7.9
Table 32
Section 11.6.5
Section 11.6.6
Figure 43 and Figure 44
Table 41, Table 41 - External
Memory Timing
Item
Item
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Add description for ZL50112
Updated IETF RFC number and standards in general
Updated the description for Stratum 3 DPLL
CPU_TS_ALE and CPU_TA. Added mode details in Figure 43
Remove STS-1 stream
Combine the packaged descriptions for all devices
Include more detailed description for the packet interface
ZL50112 and ZL50111 share the same JTAG ID
Change the title of the section
Add a note about jumbo packets
Include a paragraph to clarify the support for structure and
unstructure modes at the same time
Include more detailed description for the Payload Assembly
Add a note at the end of the section
Include more detailed description for the TDM formatter
Include more detailed description for Clock Recovery
Include more detailed description for Differential Clock
Recovery
Updated the description of Adaptive Clock Recovery
Added sub sections
TDM_HDS Input Setup and TDM_HDS Input Hold, Max. time
corrected.
Updated TXD[9:0] output delay
UpdatedSection 11.6.6 Management Interface Timing
(M_MDIO hold time and Figure 40)
and Figure 44
Added the CPU_TA assertion time.
Added Minimum Values
11
Change
Change
Data Sheet