HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 169

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy II
Timing Closure
Methodology
Altera Corporation
September 2008
The most significant impact of reduced clock tree latency is the changes
in core-to-I/O and I/O-to-core timing. For example, if an I/O register is
clocked earlier because of reduced clock latency, the arrival time of the
register output at the device pin is reduced. Similarly, if an input register
is clocked earlier, the setup time for that register is also earlier, and the
hold time requirement is relaxed.
The Quartus II software accommodates these differences to ensure that
your timing requirements are satisfied. However, you should be aware
that reduced clock insertion delay causes I/O timing differences between
your Stratix II FPGA prototype and a HardCopy II-structured ASIC.
PLL Characteristics
Many of the effects described in the
also apply to the clock outputs from PLLs between Stratix II and
HardCopy II devices. The Quartus II software implements compensation
delays for PLLs in your HardCopy II device to account for differences in
PLL clock distribution. This ensures that the compensation modes used
in the Stratix II FPGA are also used in the HardCopy II structured ASIC.
To achieve timing closure for your HardCopy II structured ASIC, it is
imperative that you use a complete set of accurate timing constraints
throughout the flow. For the Stratix II FPGA prototype, although you
may verify timing and functionality in hardware, it is essential that the
design be compiled and verified in the Quartus II software using a
complete set of timing constraints. These constraints feed forward to the
HardCopy II revision of the project, and ultimately to the HardCopy
Design Center (HCDC).
The back-end design of your structured ASIC in the HCDC ensures that
it conforms to whatever timing constraints are satisfied in the Quartus II
software. It is important to remember that while the Quartus II timing
constraints are respected, the actual Stratix II FPGA prototype timing you
observe in hardware is not duplicated in the HardCopy II structured
ASIC. The timing differences between the Stratix II device and the
HardCopy II structured ASIC are inconsequential as long as both are
checked against a complete set of timing constraints.
HardCopy II Timing Closure Flow
HardCopy II timing closure methodology is comprehensive and includes
both the TimeQuest timing analyzer and Classic Timing Analyzer in the
Quartus II software, an interface to a third-party static timing analyzer,
and FPGA-prototype timing verification in the hardware.
HardCopy II Timing Closure Methodology
“Clock Distribution Effects”
section
7–5