HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 23
HC230
Manufacturer Part Number
HC230
Description
HardCopy II Device Family
Manufacturer
ALTERA [Altera Corporation]
Datasheet
1.HC230.pdf
(228 pages)
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Altera Corporation
September 2008
3.3-V LVTTL/
LVCMOS
2.5-V LVTTL/
LVCMOS
1.8-V LVTTL/
LVCMOS
1.5-V LVCMOS
SSTL-2 class I
Table 2–9. HardCopy II Supported I/O Standards (Part 1 of 3)
I/O Standard
Single-ended
Single-ended
Single-ended
Single-ended
referenced
Voltage
Type
The IOE feature set in HardCopy II devices can be classified in one of
three categories:
■
■
■
All I/O pins in Stratix II FPGAs support general-purpose I/O standards,
which includes the LVTTL and LVCMOS I/O standards. In Stratix II
FPGAs, the PCI clamping diode and memory interfaces are supported on
the top and bottom I/O pins, while high-speed interfaces are supported
on the left and right side I/O pins of the device.
The new general purpose IOEs in HardCopy II devices are a cost saving
and area efficient advantage. The complex memory interface and the
high-speed IOE circuitry is removed to save die area while still offering
the more commonly-used features. The memory interface IOE supports
all the features available in the general purpose IOE. The high-speed IOE
also supports all the same features and I/O standards as the general
purpose IOE, except for the PCI clamping diode (supported on the
bottom general purpose IOEs in HC210 and HC220 devices).
In order to increase the I/O area efficiency of HardCopy II devices, the
features available on any given IOE depends on the location.
Table 2–9
types.
General purpose IOEs—The most commonly used I/O type in
designs.
Memory Interface IOEs—Includes features to interface with
common external memory standards.
High-speed IOEs—Supports high-speed data transmission and
reception.
shows which I/O standards are supported by the different IOE
3.3/2.5
3.3/2.5
1.8/1.5
1.8/1.5
Input
2.5
V
CCIO
Level (V)
Output
3.3
2.5
1.8
1.5
2.5
Interface
Memory
IOEs
v
v
v
v
v
Purpose IOEs
I/O Structure and Features
General
v
v
v
v
High-Speed
Preliminary
IOEs
v
v
v
v
2–15
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