AT86RF230_09 ATMEL [ATMEL Corporation], AT86RF230_09 Datasheet - Page 13

• Manufacturer Part Number: AT86RF230_09
• Description: Low Power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE and ISM
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 6-6. Example SPI Sequence - Register Access Mode
6.2.2 Frame Buffer Access Modes
Figure 6-7. Packet Structure - Frame Buffer Write Access
SCLK
MOSI
MISO
5131E-MCU Wireless-02/09
SEL
Register Write Access
WRITE COMMAND
XX
Figure 6-5. Packet Structure – Register Read Access
Each register access must be terminated by setting SEL = H.
Figure 6-6 illustrates a typical SPI sequence for a register access sequence for write
and read respectively.
The Frame Buffer read access and the Frame Buffer write access are used to upload or
download frames to the microcontroller.
Each access starts by setting SEL = L. The first byte transferred on MOSI is the
command byte and must indicate a Frame Buffer access mode according to the
definition in Table 6-2.
On Frame Buffer write access the second byte transferred on MOSI contains the frame
length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-7.
On Frame Buffer read access PHR and PSDU are transferred via MISO starting with
the second byte. After the PSDU data bytes one more byte can be transferred
containing the link quality indication (LQI) value of the received frame, for details refer
to section 8.5. Figure 6-8 illustrates the packet structure of a Frame Buffer read access.
Note, the Frame Buffer read access can be terminated at any time without any
consequences by setting SEL = H, e.g. after reading the frame length byte only.
MOSI
MISO
WRITE DATA
1
XX
byte 1 (command byte)
0
address[5:0]
XX
Register Read Access
read data[7:0]
byte 2 (data byte)
READ COMMAND
XX
XX
READ DATA
AT86RF230
XX
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