L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 3

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

Contents
Internal Register Configuration .............................................................................................................................. 75
Crystal Selection Considerations ........................................................................................................................... 81
Serial EEPROM Interface ...................................................................................................................................... 82
ac Characteristics of Serial EEPROM Interface Signals ........................................................................................ 82
NAND Tree Testing ................................................................................................................................................ 85
Solder Reflow and Handling .................................................................................................................................. 87
Absolute Maximum Voltage/Temperature Ratings ................................................................................................. 87
Electrical Characteristics ....................................................................................................................................... 88
Timing Characteristics ........................................................................................................................................... 90
Outline Diagrams ................................................................................................................................................... 91
Ordering Information .............................................................................................................................................. 91
Agere Systems Inc.
December 2005
Vendor ID Register .......................................................................................................................................... 47
Host Controller Control Register ..................................................................................................................... 48
SelfID Buffer Pointer Register ......................................................................................................................... 50
SelfID Count Register ..................................................................................................................................... 50
Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register ....................................... 51
Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register ....................................... 51
Interrupt Event (IntEvent) Register .................................................................................................................. 52
Interrupt Mask (IntMask) Register ................................................................................................................... 54
Isochronous Transmit Interrupt Event (isoXmitIntMask) Register ................................................................... 56
Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register ................................................................... 57
Isochronous Receive Interrupt Event (isoRecvIntEvent) Register .................................................................. 58
Isochronous Receive Interrupt Mask (isoRecvIntMask) Register ................................................................... 59
Fairness Control Register ............................................................................................................................... 59
Link Control Register ....................................................................................................................................... 60
Node Identification Register ............................................................................................................................ 61
PHY Core Layer Control Register ................................................................................................................... 62
Isochronous Cycle Timer Register .................................................................................................................. 62
Asynchronous Request Filter High Register ................................................................................................... 63
Asynchronous Request Filter Low Register .................................................................................................... 63
Physical Request Filter High Register ............................................................................................................. 64
Physical Request Filter Low Register ............................................................................................................. 64
Asynchronous Context Control Register ......................................................................................................... 65
Asynchronous Context Command Pointer Register ........................................................................................ 66
Isochronous Transmit Context Control (IT DMA ContextControl) Register ..................................................... 67
Isochronous Transmit Context Command Pointer Register ............................................................................ 68
Isochronous Receive Context Control (IR DMA ContextControl) Register ..................................................... 69
Isochronous Receive Context Command Pointer Register ............................................................................. 70
Isochronous Receive Context Match (IR DMA ContextMatch) Register ......................................................... 71
FW323 Vendor-Specific Registers .................................................................................................................. 72
Isochronous DMA Control ............................................................................................................................... 72
Asynchronous DMA Control ............................................................................................................................ 73
Link Options .................................................................................................................................................... 74
PHY Core Register Map .................................................................................................................................. 75
PHY Core Register Fields ............................................................................................................................... 76
Load Capacitance ........................................................................................................................................... 81
Adjustment to Crystal Loading ........................................................................................................................ 81
Crystal/Board Layout ....................................................................................................................................... 81
128-Pin TQFP ................................................................................................................................................. 91
Table of Contents
PCI PHY/Link Open Host Controller Interface
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