L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 35

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
December 2005
Internal Registers
Power Management Control and Status Register
The Power Management Control and Status register implements the control and status of the PCI power manage-
ment function. This register is not affected by the internally generated reset caused by the transition from the D3hot
to D0 state. The value of this register after a PCI reset is dependent on whether the FW323 is enabled to generate
a PME event while in the D3cold state. If the PME_D3cold bit within the Power Management Capabilities register is
asserted, then the PME_STS and PME_ENB bits within this register will not be reset by a PCI reset, i.e., these bits
will become sticky bits. Otherwise these bits, along with all the other bits within this register, will be reset by a PCI
reset.
Offset:
Default:
Type:
Reference:
Table 17. Power Management Control and Status Register Description
Agere Systems Inc.
14:13
12:9
Bit
7:5
3:2
1:0
15
8
4
48h
0000h (If PME_D3cold is deasserted)
Read/write
PCI Bus Power Management Interface Specification, Rev. 1.1, Section 3.2.4 and 1394 Open Host
Controller Interface Specification, Rev. 1.1, Section A.3.8.4
DATA_SELECT
XX00h (If PME_D3cold is asserted)
DATA_SCALE
PWR_STATE
Field Name
DYN_DATA
PME_ENB
PME_STS
Reserved
Reserved
(continued)
Type
RW PME Enable. This bit enables the function to assert PME. If this bit is
RW Power State. This 2-bit field is used to set the FW323 device power
RC This bit is set when the FW323 would normally be asserting the PME
R
R
R
R
R
signal, independent of the state of the PME_ENB bit. This bit is
cleared by a writeback of 1, and this also clears the PME signal driven
by the FW323. Writing a 0 to this bit has no effect. This bit is imple-
mented as sticky when PME_D3cold is asserted in the Power
Management Capabilities register.
This 2-bit field indicates a scaling factor that is to be used when inter-
preting the value of the PM_DATA register within the Power Manage-
ment Extension register. The value and meaning of this field will vary
depending on the value that has been selected by the DATA_SELECT
field.
This 4-bit field is used to select which data values are to be reported
through the PM_DATA field in the Power Management Extension
register and the DATA_SCALE fields. Valid values are 0—7, which
map to power consumption/dissipation ratings for the FW323 within
the PM_DATA/DATA_SCALE fields.
cleared, then assertion of PME is disabled. This bit is implemented as
sticky when PME_D3cold is asserted in the Power Management
Capabilities register.
Reserved. Bits 7:5 return 0s when read.
Dynamic Data. This bit returns 0 when read, since the FW323 does
not report dynamic data.
Reserved. Bits 3:2 return 0s when read.
state and is encoded as follows:
00 = current power state is D0.
01 = current power state is D1.
10 = current power state is D2.
11 = current power state is D3.
PCI PHY/Link Open Host Controller Interface
Description
FW323 06 1394a
35