74ACT138SJ Fairchild Semiconductor, 74ACT138SJ Datasheet - Page 2

DECODER/DEMUX 1-OF-8 16SOP

74ACT138SJ

Manufacturer Part Number
74ACT138SJ
Description
DECODER/DEMUX 1-OF-8 16SOP
Manufacturer
Fairchild Semiconductor
Series
74ACTr
Type
Decoder/Demultiplexerr
Datasheet

Specifications of 74ACT138SJ

Circuit
1 x 3:8
Independent Circuits
1
Current - Output High, Low
24mA, 24mA
Voltage Supply Source
Single Supply
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ACT138SJ
Manufacturer:
NS
Quantity:
913
www.fairchildsemi.com
Truth Table
H
Functional Description
The AC/ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A
when enabled, provides eight mutually exclusive active-
LOW outputs (O
Enable inputs, two active-LOW (E
HIGH (E
LOW and E
easy parallel expansion of the device to a 1-of-32 (5 lines
to 32 lines) decoder with just four AC/ACT138 devices and
one inverter (see Figure 1). The AC/ACT138 can be used
as an 8-output demultiplexer by using one of the active
LOW Enable inputs as the data input and the other Enable
inputs as strobes. The Enable inputs which are not used
must be permanently tied to their appropriate active-HIGH
or active-LOW state.
HIGH Voltage Level
3
). All outputs will be HIGH unless E
3
is HIGH. This multiple enable function allows
E
H
X
X
L
L
L
L
L
L
L
L
1
0
–O
E
7
H
X
X
L
L
L
L
L
L
L
L
). The AC/ACT138 features three
2
L
LOW Voltage Level
E
X
X
H
H
H
H
H
H
H
H
L
Inputs
3
1
A
X
X
X
H
H
H
H
L
L
L
L
, E
0
FIGURE 1. Expansion to 1-of-32 Decoding
2
) and one active-
0
A
H
H
H
H
X
X
X
L
L
L
L
, A
1
1
1
and E
X
, A
A
X
X
X
H
H
H
H
L
L
L
L
Immaterial
2
2
) and,
2
are
O
H
H
H
H
H
H
H
H
H
H
L
0
2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
O
H
H
H
H
H
H
H
H
H
H
L
1
O
H
H
H
H
H
H
H
H
H
H
L
2
O
Outputs
H
H
H
H
H
H
H
H
H
H
L
3
O
H
H
H
H
H
H
H
H
H
H
L
4
O
H
H
H
H
H
H
H
H
H
H
L
5
O
H
H
H
H
H
H
H
H
H
H
L
6
O
H
H
H
H
H
H
H
H
H
H
L
7

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