HV6506PJ Supertex, HV6506PJ Datasheet
HV6506PJ
Manufacturer Part Number
HV6506PJ
Description
PLCC44
Manufacturer
Supertex
Specifications of HV6506PJ
Date_code
10+
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HV6506PJ
Manufacturer:
SUPERTEX
Quantity:
12 388
Part Number:
HV6506PJ
Manufacturer:
SUPERTE
Quantity:
20 000
Ordering Information
Features
Absolute Maximum Ratings
Supply voltage, V
Output voltage, V
Logic input levels
Ground current
Continuous total power dissipation
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Notes:
1. Device will survive (but operation may not be specified or guaranteed) at
2. All voltages are referenced to V
3. Duty cycle is limited by the total power dissipated in the package.
4. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.
these extremes.
Device
Processed with HVCMOS
32 push-pull CMOS output up to 60V
Low power level shifting
Source/sink current minimum 5mA
Shift register speed 5MHz
Latched data outputs
Bidirectional shift register (DIR)
Backplane output
HV6506
3
2
PP
DD
2
2
Plastic Chip Carrier
44-J Lead Quad
SS
HV6506PJ
.
®
technology
with Separate Backplane Output
4
32-Channel LCD Driver
-0.5V to V
-65°C to +125°C
-40°C to +85°C
-0.5V to +7.0V
-0.5V to +80V
1
DD
1200mW
+ 0.5V
260°C
1.5A
12-132
Package Options
Plastic Gullwing
General Description
The HV65 is a low-voltage serial to high-voltage parallel converter
with push-pull outputs. This device has been designed for use as
a driver circuit for LCD displays. It can also be used in any
application requiring multiple output high-voltage current sourc-
ing and sinking capabilities. The inputs are fully CMOS compat-
ible.
The device consists of a 32-bit shift register, 32 latches, and
control logic to perform the polarity select of the outputs. HVout1
is connected to the first stage of the shift register through the
polarity logic. Data is shifted through the shift register on the logic
low to high transition of the clock. A DIR pin causes data shifting
counterclockwise when grounded and clockwise when connected
to V
This output reflects the current status of the last bit of the shift
register. Operation of the shift register is not affected by the LE
(latch enable) or the POL (polarity) inputs. Transfer of data from
the shift register to the latch occurs when the LE (latch enable)
input is high. The data in the latch is stored after LE transition from
high to low.
44 Lead Quad
HV6506PG
DD
. A data output buffer is provided for cascading devices.
in waffle pack
HV6506X
HV6506
Dice
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