K9F1G08D0M SAMSUNG [Samsung semiconductor], K9F1G08D0M Datasheet - Page 32

• Manufacturer Part Number: K9F1G08D0M
• Description: 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F1G08Q0M
K9F1G08D0M
K9F1G08U0M K9F1G16U0M
Figure 7. Random Data Output In a Page
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive
bytes up to 2112(X8 device) or words up to 1056(X16 device), in a single page program cycle. The number of consecutive partial
page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(X8
device:1time/512byte, X16 device:1time/256word) and 4 times for spare array(X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which
up to 2112bytes(X8 device) or 1056words(X16 device) of data may be loaded into the data register, followed by a non-volatile pro-
gramming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address inputs and
then serial data loading. The words other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data
input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and tim-
ings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a pro-
gram cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
R/B
RE
I/Ox
R/B
I/Ox
00h
80h
Col Add1,2 & Row Add1,2
K9F1G16Q0M
K9F1G16D0M
Address
4Cycles
Col Add1,2 & Row Add1,2
Address & Data Input
Data
30h
t
R
Data Field
10h
Data Output
32
Spare Field
t
PROG
05h
Address
2Cycles
70h
FLASH MEMORY
E0h
Data Field
I/O
Fail
Data Output
0
"1"
"0"
Spare Field
Pass