HYS6472V16200GU SIEMENS [Siemens Semiconductor Group], HYS6472V16200GU Datasheet
HYS6472V16200GU
Related parts for HYS6472V16200GU
HYS6472V16200GU Summary of contents
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... SDRAM Modules 3.3 V 64M 64/72-Bit SDRAM Modules PC100-168 pin unbuffered DIMM Modules Preliminary Information • 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications • One bank 16M 64, 16M • Two bank 32M 64, 32M • Optimized for byte-write non-parity or ECC applications • ...
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... The HYS 64/72V1600, HYS 64/72V32220, HYS 64/72V32200 and HYS 64/72V64220 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 16M 16M 72, 32M 64 and 32M two banks high speed memory arrays designed with 128M and 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications ...
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... SCL SDA N. Rows Columns Bank Select SDRAM Modules Module Height 64 1 bank 1.25“ bank 1.25“ bank 1.25“ bank 1.25“ Clock Input Data Mask Chip Select Power (+ 3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence ...
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... A5 V 120 A7 SS CLK2 121 A9 NC 122 BA0 WP 123 A11 SDA 124 V CC SCL 125 CLK1 126 A12 SDRAM Modules PIN # Symbol 127 V SS 128 CKE0 129 CS3 130 DQMB6 131 DQMB7 132 NC 133 V CC 134 NC 135 NC 136 CB6 137 ...
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... DQ(39:32 DQMB5 DQ(47:40 DQMB6 DQ(55:48 DQMB7 DQ(63:56) D3 D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) CLK0 CLK1 CLK2 CLK3 64/72 one bank SDRAM DIMM Modules 5 SDRAM Modules CS WE DQM DQ0-DQ7 DQM DQ0-DQ7 DQM DQ0-DQ7 DQM DQ0-DQ7 D7 E PROM (256 word x 8 Bit) 2 SA0 SA0 ...
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... DQ(47:40 DQM DQ0-DQ7 D16 D17 CS DQM DQMB6 DQ0-DQ7 DQ(55:48) D2 D10 CS DQM DQMB7 DQ0-DQ7 DQ(63:56) D3 D11 CLK0 CLK1 CLK2 CLK3 64/72 two bank SDRAM DIMM Modules 6 SDRAM Modules CS CS DQM DQM DQ0-DQ7 DQ0-DQ7 DQM DQM DQ0-DQ7 DQ0-DQ7 DQM DQM DQ0-DQ7 DQ0-DQ7 ...
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... MHz Symbol max. 32M ICL SDRAM Modules Symbol Limit Values min. max – 0.5 0 2.4 – – 0 – I(L) I – O(L) Limit Values max. ...
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... and assumed and the Semiconductor Group HYS 64(72)V16200/3222(0)0/64220GU 1 0 min min CKE IH(MIN.) V CKE IL(MAX.) – – standard version = infinity DDQ 8 SDRAM Modules Symb. -8/-8B -10 Unit Note max. I CC1 4 210 165 mA 8 210 165 mA 16 210 165 CC2P I 19 ...
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... – RCD t 70 – – RAS t 20 – – RRD t 1 – CCD 9 SDRAM Modules Limit Values Unit -8B PC100-323 min. max. 10 – – ns – 100 MHz – 83 MHz – – – – ...
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... A SS Parameter Refresh Cycle Self Refresh Exit Time Refresh Period Refresh Interval 128Mbit SDRAM based modules 256Mbit SDRAM based modules Read Cycle Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency ...
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... 1 SPT03404 t /2 – 0.5) ns has to be added to this parameter – has to be added to this parameter SDRAM Modules V V and . All AC measurements and t parameters are Measurement conditions for 1 and AC OH ...
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... A serial presence detect storage device - E about the module configuration, speed, etc. is written into the E production using a serial presence detect protocol (I SPD-Table for 256MBit SDRAM based PC100 Modules Byte# Description 0 Number of SPD bytes 1 Total bytes in Serial PD 2 Memory Type 3 Number of Row Addresses ...
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... SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d) Byte# Description 18 Supported CAS Latencies 19 CS Latencies 20 WE Latencies 21 SDRAM DIMM module attributes 22 SDRAM Device Attributes: General 23 Min. Clock Cycle Time at CAS Latency = 2 24 Max. data access time from Clock for ...
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... SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d) Byte# Description 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 64- Manufacturers 125 information (optional) (FF if not used) H 126 Frequency Specification 127 100 MHz support details 128+ Unused storage locations – ...
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... SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d) Byte# Description 10 SDRAM Access time from Clock Dimm Configuration 12 Refresh Rate/Type 13 SDRAM width, Primary 14 Error Checking SDRAM data width 15 Minimum clock delay for back-to-back random column address 16 Burst Length supported ...
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... SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d) Byte# Description 28 Minimum Row Active to t Row Active delay RRD 29 Minimum RAS to CAS delay t RCD 30 Minimum RAS pulse t width RAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time ...
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... Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group HYS 64(72)V16200/3222(0)0/64220GU 133.35 127. 6.35 42. 1.27 = 115.57 124 125 *) 17 SDRAM Modules 4 84 1.27 ± 0.1 168 2. ECC modules only GLD09159 Dimensions in mm 1998-08-01 ...