HYS6472V16200GU SIEMENS [Siemens Semiconductor Group], HYS6472V16200GU Datasheet - Page 15
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HYS6472V16200GU
Manufacturer Part Number
HYS6472V16200GU
Description
3.3 V 16M x 64/72-Bit SDRAM Modules 3.3 V 32M x 64/72-Bit SDRAM Modules 3.3 V 64M x 64/72-Bit SDRAM Modules
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.HYS6472V16200GU.pdf
(17 pages)
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte# Description
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Semiconductor Group
SDRAM Access time
from Clock at CL = 3
Dimm Configuration
Refresh Rate/Type
SDRAM width, Primary
Error Checking SDRAM
data width
Minimum clock delay for
back-to-back random
column address
Burst Length supported
Number of SDRAM
banks
Supported CAS
Latencies
CS Latencies
WE Latencies
SDRAM DIMM module
attributes
SDRAM Device
Attributes: General
Min. Clock Cycle Time at
CAS Latency = 2
Max. data access time
from Clock for CL = 2
Minimum Clock Cycle
Time at CL = 1
Maximum Data Access
Time from Clock at
CL = 1
Minimum Row Precharge
Time
SPD Entry
Value
6.0 ns
none/ECC
Self Refresh,
7.8 s
n/a/ 8
t
1, 2, 4, 8 & full
page
4
CAS latency = 2
& 3
CS latency = 0
Write latency = 0 01
non buffered/
non re.
V
10.0/12.0 ns
6.0/7.0 ns
not supported
not supported
20/30 ns
CCD
CC
8
tol
= 1 CLK
10%
15
HYS 64(72)V16200/3222(0)0/64220GU
64M 64
two bank
-8
60
00
82
08
00
01
8F
04
06
01
00
06
A0
60
FF
FF
14
64M 64
two bank
-8B
60
00
82
08
00
01
8F
04
06
01
01
00
06
C0
70
FF
FF
1E
Hex
SDRAM Modules
64M 72
two bank
-8
60
02
82
08
08
01
8F
04
06
01
01
00
06
A0
60
FF
FF
14
1998-08-01
64M 72
two bank
-8B
60
02
82
08
08
01
8F
04
06
01
01
00
06
C0
70
FF
FF
1E