HYS64T128920EU-2.5-B2 QIMONDA [Qimonda AG], HYS64T128920EU-2.5-B2 Datasheet - Page 21

• Manufacturer Part Number: HYS64T128920EU-2.5-B2
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3.2
DRAM Component Timing Parameters:
Rev. 1.0, 2006-10
10202006-L0SM-FEYT
Parameter
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
DQ and DM input setup time
DQ and DM input hold time
Control & address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
DQS-DQ skew for DQS & associated DQ signals
CK half pulse width
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to DQS associated clock edges
DQS latching rising transition to associated clock
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
CAS to CAS command delay
Write recovery time
Auto-Precharge write recovery + precharge time
Internal write to read command delay
DRAM Component Timing Parameters
Table 15
DRAM Component Timing Parameter by Speed Grade - DDR2–800
for DDR2–800;
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
DQSCK
CH.AVG
CL.AVG
CK.AVG
DS.BASE
DH.BASE
IPW
DIPW
HZ
LZ.DQS
LZ.DQ
DQSQ
HP
QHS
QH
DQSS
DQSH
DQSL
DSS
DSH
WPST
WPRE
IS.BASE
IH.BASE
RPRE
RPST
CCD
WR
DAL
WTR
21
Table 16
DDR2–800
–400
–350
0.48
0.48
2500
50
125
0.6
0.35
—
t
2 x
—
Min(
t
—
t
RL – 1
– 0.25
0.35
0.35
0.2
0.2
0.4
0.35
175
250
0.9
0.4
2
15
WR +
7.5
Min.
AC.MIN
CL.ABS
HP
HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2
–
t
AC.MIN
t
CH.ABS
t
)
QHS
t
nRP
for DDR2–667 and
,
+400
+350
0.52
0.52
8000
––
––
—
—
—
—
—
—
0.6
—
—
—
1.1
0.6
—
—
—
Max.
t
t
t
200
__
300
—
+ 0.25
—
AC.MAX
AC.MAX
AC.MAX
Unbuffered DDR2 SDRAM Module
Table 17
Unit
ps
ps
t
t
ps
ps
ps
t
t
ps
ps
ps
ps
ps
ps
ps
nCK
t
t
t
t
t
t
t
ps
ps
t
t
nCK
ns
nCK
ns
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Internet Data Sheet
for DDR2–533C.
TABLE 15
Note
8)
9)
9)
10)11)
10)11)
10)11)
12)13)14)
13)14)15)
9)16)
9)16)
9)16)
17)
18)
19)
20)
21)
21)
21)
22)23)
23)24)
25)26)
25)27)
1)
28)29)
1)30)
1)2)3)4)5)6)7)