HYS64T128920EU-2.5-B2 QIMONDA [Qimonda AG], HYS64T128920EU-2.5-B2 Datasheet - Page 30

• Manufacturer Part Number: HYS64T128920EU-2.5-B2
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

13) The
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
15) 0 °C≤
16) 85 °C <
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The
19) The maximum limit for the
20) WR must be programmed to fulfill the minimum requirement for the
21) Minimum
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
3.3.3
ODT AC Character. & Operating Conditions:
1) New units, '
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Rev. 1.0, 2006-10
10202006-L0SM-FEYT
Symbol
t
t
t
t
t
t
t
t
AOND
AON
AONPD
AOFD
AOF
AOFPD
ANPD
AXPD
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
Compliant Products” on Page
performance (bus turnaround) degrades accordingly.
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, '
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 ×
ODT resistance is fully on. Both are measured from
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
Both are measured from
3 ns is assumed,
LOW and by counting the actual input clock edge.
t
HZ,
t
t
t
HZ
RPST
RRD
T
,
CASE
T
t
RPST
), or begins driving (
timing parameter depends on the page size of the DRAM organization. See
CASE
t
Parameter / Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Modes)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
WTR
t
t
CK.AVG
≤ 85 °C
CK
and
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
' is used for both concepts. Example:
t
t
' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit '
AOFD
LZ
ODT AC Electrical Characteristics
,
t
RPRE
= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
t
XARDS
t
AOFD
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
t
t
DAL
. Both are measured from
LZ,
has to be satisfied.
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
4.
= WR + (
RPRE
).
ODT AC Character. and Operating Conditions for DDR2-667 & DDR2-800
t
HZ
t
RP
and
/
t
Table 18
CK
t
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
transitions occur in the same access time windows as valid data transitions.These
t
AOND
t
XP
t
CK.AVG
t
= 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
AOFD
, which is interpreted differently per speed bin. For DDR2-667/800,
for DDR2–667 & DDR2–800 and
+
t
XARD
, which is interpreted differently per speed bin. For DDR2-667/800,if
t
EPR.2PER(MIN)
Values
Min.
2
t
t
2.5
t
t
3
8
AC.MIN
AC.MIN
AC.MIN
AC.MIN
30
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
t
WR
timing parameter, where
+ 2 ns
+ 2 ns
HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2
.
t
CK.AVG
Max.
2
t
2
t
2.5
—
—
2.5
AC.MAX
AC.MAX
t
Table 2 “Ordering Information for RoHS
CK +
' represents the actual
t
CK +
t
+ 0.7 ns
AC.MAX
+ 0.6 ns
t
Unbuffered DDR2 SDRAM Module
AC.MAX
Table 19
WR
+ 1 ns
MIN
+ 1 ns
[cycles] =
for DDR2–533 & DDR2–400
t
CK.AVG
Internet Data Sheet
Unit
nCK
ns
ns
nCK
ns
ns
nCK
nCK
t
WR
(ns)/
TABLE 18
of the input clock
t
CK
t
AOND
(ns) rounded
Note
1)
1)2)
1)
1)
1)3)
1)
1)
1)
is 2 clock
t
CK.AVG
t
CK
=