HYS64T128920HU QIMONDA [Qimonda AG], HYS64T128920HU Datasheet - Page 19

• Manufacturer Part Number: HYS64T128920HU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
input reference level is the crosspoint when in differential strobe mode.
t
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
input reference level is the crosspoint when in differential strobe mode.
t
RAS.MAX
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 3
@ CL = 4
@ CL = 5
V
V
REF
REF
V
V
stabilizes. During the period before
stabilizes. During the period before
TT
TT
.
.
Symbol
t
t
t
t
t
t
t
Symbol
t
t
t
t
t
t
t
CK
CK
CK
RAS
RC
RCD
RP
CK
CK
CK
RAS
RC
RCD
RP
19
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade Definition Speed Bins for DDR2–400B
DDR2–533C
–3.7
4–4–4
Min.
5
3.75
3.75
45
60
15
15
DDR2–400B
–5
3–3–3
Min.
5
5
5
40
55
15
15
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
V
V
REF
REF
stabilizes, CKE = 0.2 x
stabilizes, CKE = 0.2 x
Max.
8
8
8
70000
—
—
—
Max.
8
8
8
70000
—
—
—
Unbuffered DDR2 SDRAM Modules
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
CK
CK
V
V
DDQ
DDQ
Internet Data Sheet
is recognized as low.
is recognized as low.
TABLE 15
TABLE 16
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
t
t
REFI
REFI
.
.