HYS64T128920HU QIMONDA [Qimonda AG], HYS64T128920HU Datasheet - Page 20

• Manufacturer Part Number: HYS64T128920HU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3.2
List of AC Timing parameters.
•
•
•
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
Parameter
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
DQ and DM input setup time
DQ and DM input hold time
Control & address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
DQS-DQ skew for DQS & associated DQ signals
CK half pulse width
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to DQS associated clock edges
DQS latching rising transition to associated clock
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to precharge command
Table 17 “Timing Parameter by Speed Grade - DDR2–667” on Page 20
Table 18 “Timing Parameter by Speed Grade - DDR2–533” on Page 25
Table 19 “Timing Parameter by Speed Grade - DDR2-400” on Page 28
AC Timing Parameters
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WL
t
t
t
t
t
t
t
t
t
t
t
t
AC
DQSCK
CH.AVG
CL.AVG
CK.AVG
DS.BASE
DH.BASE
IPW
DIPW
HZ
LZ.DQS
LZ.DQ
DQSQ
HP
QHS
QH
DQSS
DQSH
DQSL
DSS
DSH
WPST
WPRE
LS.BASE
LH.BASE
RPRE
RPST
RAS
20
DDR2–667
–450
–400
0.48
0.48
3000
100
175
0.6
0.35
—
t
2 x
—
Min(
t
—
t
RL–1
– 0.25
0.35
0.35
0.2
0.2
0.4
0.35
200
275
0.9
0.4
45
Min.
Timing Parameter by Speed Grade - DDR2–667
AC.MIN
CL.ABS
HP
–
t
AC.MIN
t
CH.ABS
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
t
)
QHS
,
+450
+400
0.52
0.52
8000
––
––
—
—
—
—
—
—
0.6
—
—
—
1.1
0.6
70000
Max.
t
t
t
240
__
340
—
+ 0.25
AC.MAX
AC.MAX
AC.MAX
Unbuffered DDR2 SDRAM Modules
Unit
ps
ps
t
t
ps
ps
ps
t
t
ps
ps
ps
ps
ps
ps
ps
nCK
t
t
t
t
t
t
t
ps
ps
t
t
ns
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Internet Data Sheet
TABLE 17
Notes
7)8)
9)
9)
10)11)
10)11)
12)13)14)
13)14)15)
9)16)
9)16)
9)16)
17)
18)
19)
20)
21)
21)
21)
22)23)
23)24)
25)26)
25)27)
28)
1)2)3)4)5)6)