PPC440EPX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440EPX-NPAFFFTS Datasheet - Page 11

• Manufacturer Part Number: PPC440EPX-NPAFFFTS
• Description: PowerPC 440EPx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 1.26 – October 15, 2007
PowerPC 440 Processor
The PowerPC 440 processor is designed for high-end applications: RAID controllers, SAN, iSCSI, routers,
switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the
128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
Floating Point Unit (FPU)
The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers
single cycle through put on most instructions.
Features include:
SRAM Controller
The internal SRAM controller (ISC) supports the following features:
AMCC Proprietary
Preliminary Data Sheet
• Up to 667 MHz operation
• PowerPC Book E architecture
• 32 KB I-cache, 32 KB D-cache
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64 GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit
• Debug facilities
• 24 DSP instructions
• Five stages with 2 MFlops/Hz
• Hardware support for IEEE 754
• Single- and double-precision
• Single-cycle throughput on most instructions
• Thirty-two 64-bit floating point registers
• One bank (Bank 0) of 16 KB configurable as 4 KB, 8 KB or 16 KB (128 bits wide)
• 128-bit slave attachment addressable by any PLB master
• Transfers by PLB slave cycles:
– UTLB Word Wide parity on data and tag address parity with exception force
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
– Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters)
– 4-word line read and write
– 8-word line read and write
– Double word read and write bursts for 64-bit masters
– Quadword read and write bursts for 128-bit masters
440EPx – PPC440EPx Embedded Processor
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