PSD913G2 STMICROELECTRONICS [STMicroelectronics], PSD913G2 Datasheet - Page 32

• Manufacturer Part Number: PSD913G2
• Description: Configurable Memory System on a Chip for 8-Bit Microcontrollers
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

PSD935G2
The
PSD935G2
Functional
Blocks
(cont.)
Bit Definition
Memory_ID0 Register
Bit Definition
Memory_ID1 Register
9.1.5 Memory ID Registers
The 8-bit read only memory status registers are included in the CSIOP space. The user
can determine the memory configuration of the PSD device by reading the Memory ID0
and Memory ID1 registers. The content of the registers are defined as follow:
*
Not used bit should be set to zero.
S_size 3
Bit 7
Bit 7
B_type1
B_size3
F_size3
S_size3
*
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
S_size 2
Bit 6
Bit 6
*
B_type0
B_size2
S_size2
F_size2
B_type 1
S_size 1
Bit 5
0
0
0
0
Bit 5
0
0
0
0
0
1
0
0
0
0
1
1
1
B_type 0
S_size 0
Bit 4
Bit 4
Boot Block Type
EEPROM
B_size1
F_size1
S_size1
Flash
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
F_size 3
B_size 3
Bit 3
Bit 3
F_size 2
B_size 2
B_size0
S_size0
F_size0
Bit 2
Bit 2
PSD9XX Family
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
F_size 1
B_size 1
Bit 1
Bit 1
Boot Block Size
Main Flash Size
SRAM Size
128K
256K
512K
256K
512K
none
none
none
(Bit)
(Bit)
(Bit)
16K
32K
64K
1M
2M
4M
8M
B_size 0
F_size 0
Bit 0
Bit 0
31