ISL6612 INTERSIL [Intersil Corporation], ISL6612 Datasheet - Page 9

• Manufacturer Part Number: ISL6612
• Description: Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features
• Manufacturer: INTERSIL [Intersil Corporation]

maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room temperature,
while the power dissipation capacity in the EPSOIC and DFN
packages, with an exposed heat escape pad, is more than
2W and 1.5W, respectively. Both EPSOIC and DFN
packages are more suitable for high frequency applications.
See Layout Considerations paragraph for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with EQs. 2 and 3, respectively,
where the gate charge (Q
particular gate to source voltage (V
corresponding MOSFET datasheet; I
quiescent current with no load at both drive outputs; N
and N
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
(R
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
P
I
DR
Qg_TOT
GI1
P
P
=
Qg_Q1
Qg_Q2
Q2
and R



Q
----------------------------------------------------- -
are number of upper and lower MOSFETs,
=
G1
G1
P
GI2
=
•
=
Qg_Q1
UVCC N
V
and R
Q
-------------------------------------- - F
Q
------------------------------------- - F
) of MOSFETs. Figures 3 and 4 show the
GS1
G1
G2
V
V
•
•
+
GS2
GS1
•
G2
UVCC
LVCC
P
Qg_Q2
) and the internal gate resistors
Q1
G1
+
2
2
•
Q
---------------------------------------------------- -
and Q
•
+
9
G2
I
SW
Q
SW
•
•
LVCC N
•
VCC
V
GS1
G2
•
N
GS2
N
Q
Q2
) is defined at a
Q1
and V
is the driver’s total
•
Q2
GS2



Q*
•
VCC
) in the
F
SW
ISL6612, ISL6613
(EQ. 2)
(EQ. 3)
+
Q1
I
Q
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
P
P
P
R
DR
DR_UP
DR_LOW
EXT1
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
UVCC
=
LVCC
P
=
DR_UP
=
R
=



G1
PHASE
--------------------------------------
R



R
HI1
--------------------------------------
R
R
+
BOOT
LO2
HI2
R
HI2
R
+
R
-------------
R
N
LO1
HI1
+
P
GI1
HI1
R
Q1
DR_LOW
R
+
HI2
EXT1
R
EXT2
+
+
+
--------------------------------------- -
R
I
LO1
--------------------------------------- -
R
R
R
Q
LO2
G2
EXT2
R
•
R
G
G1
VCC
+
LO1
R
G
R
+
LO2
R
C
EXT1
R
GI2
R
GD
=
C
EXT2
C
GI1
GD
R
GS
C
G2
GS



•



S
+
P
---------------------
•
S
R
-------------
N
Qg_Q1
P
---------------------
GI2
Qg_Q2
Q2
2
D
2
D
Q2
C
July 25, 2005
Q1
DS
C
FN9153.5
(EQ. 4)
DS