LIS302DL_08 STMICROELECTRONICS [STMicroelectronics], LIS302DL_08 Datasheet - Page 31

• Manufacturer Part Number: LIS302DL_08
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

LIS302DL
7.11
7.12
FF_WU_SRC_1 (31h)
Table 33.
Table 34.
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and
allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was
chosen.
FF_WU_THS_1 (32h)
Table 35.
Table 36.
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
IA
ZH
ZL
YH
YL
XH
XL
THS6, THS0
DCRM
X
DCRM
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one ore more interrupt has been generated)
Z high. Default value: 0
(0: no interrupt, 1: ZH event has occurred)
Z low. Default value: 0
(0: no interrupt; 1: ZL event has occurred)
Y high. Default value: 0
(0: no interrupt, 1: YH event has occurred)
Y low. Default value: 0
(0: no interrupt, 1: YL event has occurred)
X high. Default value: 0
(0: no interrupt, 1: XH event has occurred)
X low. Default value: 0
(0: no interrupt, 1: XL event has occurred)
FF_WU_SRC_1 (31h) register
FF_WU_SRC_1 (31h) register description
FF_WU_THS_1 (32h) register
FF_WU_THS_1 (32h) register description
THS6
IA
Resetting mode selection. Default value: 0
(0: counter resetted; 1: counter decremented)
Free-fall / wake-up threshold: default value: 000 000x
THS5
ZH
THS4
ZL
THS3
YH
THS2
YL
Register description
THS1
XH
THS0
XL
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