R8A66171SP RENESAS [Renesas Technology Corp], R8A66171SP Datasheet - Page 4

• Manufacturer Part Number: R8A66171SP
• Description: A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66171DD/SP
PIN DESCRIPTIONS
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 4 of 22
RESET
D0~D7
CTS
RTS
RxD
C/D
WR
TxD
INT
Pin
CS
RD
X1
X2
P0
P1
Transmission data output
Request-to-send output
Command/Data control
Reception data input
Clear-to-send input
Read control input
Write control input
Chip select input
Interrupt output
Clock output
Reset input
Clock input
Port output
Port output
Data bus
Name
input
Output
Output
Output
Output The serial data is transmitted from this pin.
Output
Output
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
I/O
A crystal is externally connected to these pins for generating an
internal clock. An external clock signal can be input to X1 instead of
a crystal. Then X2 output opened.
This reset is a master reset, therefore commands should be loaded
after the reset.
A low level signal on the chip select input enables the R8A66171.
The device can not be accessed when the signal is high-level.
This signal distinguishes whether the information on the R8A66171
data bus is data, command or status information. When the signal
is high-level, the data bus has command or status information.
When the signal is low-level, the data bus has data.
The receiving data or status information is output to the data bus
from the R8A66171 by a low-level signal.
The data or command output from the MCU is written to the
R8A66171 by a low-level signal.
This is an 8-bit bi-directional bus buffer. Command, status
information, and transfer data are transferred to/from the MCU via
this data bus buffer.
This is used as an interrupt request to MCU. The interrupt request
is generated when the receive FIFO is full, the transmit FIFO is
empty or the block reception is complete. D2 bit of command 6
controls the switching of low-level and high-level interrupt.
The serial data is sent to this pin.
This is an ordinary port pin. This pin is controlled by the D0 bit of
command 6.
This pin has the same function as that of P0 pin and provides
information of packet transmission's completion. The switching of
this function is controlled by command 6, D1 bit.
When the TXEN bit (D0) of command 4 is set to 1 and the /CTS
input is low-level, serial data is sent from the TxD pin. This is used
as the clear-to-send signal.
This is used as the request-to-send signal. This pin is controlled by
the D3 bit of command 4.
Function