R8A66171SP RENESAS [Renesas Technology Corp], R8A66171SP Datasheet - Page 5

• Manufacturer Part Number: R8A66171SP
• Description: A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66171DD/SP
DISCRIPTION OF FUNCTION
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 5 of 22
● Baud rate generator
● Block length counter
● Transmit data buffer (FIFO)
The 8-bit programmable divider (baud rate generator) generates the baud rate for transmit or receive.
The division rate is (n+1) with a range of n=0~255. The baud rate is calculated by the following
formula:
The R8A66171 can handle multiple-bytes of data as one block (packet).
Therefore, CRC of bytes is possible. The block length counter is a 6-bit programmable counter. The
block length is (m+1) bytes with the allowed values of m=0~63.
The prescaler division rate is set by the D0 bit of command1. The baud rate generator division rate is
set by command2.
Example as follows:
The transmit data buffer (FIFO) consists of 4-bytes.
The transmit data buffer (FIFO) functions according to the block length.
When a block of data is written to the transmit data buffer (FIFO), /CTS is low-level and TXEN is high-
level, the data in the transmit data buffer (FIFO) is sent to the transmit buffer. If /CTS is high-level
while data is transmitted, all data is transmitted (including the data in the transmit data buffer (FIFO)).
When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the
transmit buffer until MCU writes a new block of data to the transmit data buffer (FIFO). The MCU can
not write new data to the transmit data buffer (FIFO) until the buffer becomes empty.
Block length=1~3
When the transmit data buffer (FIFO) becomes empty (buffer empty) and /INT is set to low-active, the
interrupt output /INT is set to a low-level. The MCU verifies the buffer is empty when the D2 bit of the
status1 information is read. The MCU should write the block length data to the transmit data buffer
(FIFO) at this moment.
Block length=4 or more
When the transmit data buffer (FIFO) becomes empty and /INT is set low-active, the interrupt output
/INT becomes low. The MCU verifies the buffer is empty by reading the D2 bit of the status1
information.
When this happens, the MCU should write the 4-bytes of data to the transmit data buffer (FIFO). The
data in the transmit data buffer (FIFO) is sent to the transmit buffer when /CTS is low-level and TXEN
is high-level. When the number of bytes from the MCU becomes less than 4 at the last stage of the
block transmission, the same operation should be made as the block length=1~3.
When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the
transmit buffer until MCU writes data of the fixed block length to the transmit data buffer (FIFO). The
MCU cannot write data to the transmit data buffer (FIFO) until the buffer becomes empty.
Example : Block length=2
MCU
9600bps
baud rate =
Transmit data buffer(FIFO)
DATA DATA
=
2・(31+1)・16
prescaler division (2 or 32)・baud rate generator division rate (n+1)・16
9.8304MHz
Transmit buffer(P → S)
f(X1)
TxD pin