R8A66171SP RENESAS [Renesas Technology Corp], R8A66171SP Datasheet - Page 6

• Manufacturer Part Number: R8A66171SP
• Description: A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
• Manufacturer: RENESAS [Renesas Technology Corp]

R8A66171DD/SP
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 6 of 22
● Receive data buffer (FIFO)
The receive data buffer (FIFO) consists of 4-bytes. The receive data buffer (FIFO) functions according
to the block length.
Block length=1~3
When the data of the block length is received and /INT is set to low-level, the interrupt output /INT
becomes low-level. The MCU acknowledges the packet end by setting the D0 bit of the status1
information.
In this case, the MCU should read all data from the receive data buffer (FIFO).
At the packet end, the data from the receive buffer cannot be transmitted to the receive data buffer
(FIFO) until the MCU reads all data in the receive data buffer (FIFO). The MCU cannot read data in
the receive data buffer until the packet end.
Block length=4 or more
When 4-byte data enters the receive data buffer (FIFO) (buffer full) and /INT is set to low-active, the
interrupt output /INT becomes low-level. The MCU acknowledges the buffer full status by setting the
D1 bit of the status1 information.
In this case, the MCU should read all data in the receive data buffer (FIFO).
When the last data enters the receive data buffer (FIFO), the packet end becomes the same operation
as for 1~3 byte block length. If the block length is a multiple of four, the D0 and D1 bits of the status1
information are set when the last data enters the receive data buffer (FIFO). At packet end or buffer
full, the new data cannot be transferred from the receive buffer to the receive data buffer (FIFO). The
MCU cannot read data in the receive data buffer (FIFO) until packet end or buffer full occurs.
Example : Block length=6
Example : Block length=6
Example : Block length=2
MCU
MCU
MCU
Receive data buffer(FIFO)
(Second interrupt-packet end)
Transmit data buffer(FIFO)
Receive data buffer(FIFO)
(First interrupt-buffer full)
Transmit data buffer(FIFO)
DATA DATA
Receive data buffer(FIFO)
(Interrupt-packet end)
DATA DATA
DATA DATA
DATA DATA
DATA DATA
or
or
DATA DATA
DATA DATA
Transmit buffer(P → S)
Receive buffer(P ← S)
Receive buffer(P ← S)
TxD pin
RxD pin
RxD pin