ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 38

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
RapidIO Interface to Pi-Sched
Table 9. Signals Used as Register Bits
Memory Map
Definition of Register Types
There are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. There are no mixed registers in
the chip. This means that all bits of a particular register (particular address) are structurally the same. All of these
registers are accessed via the FPGA system bus which, in turn, can be accessed by the MPI block or through
FPGA logic.
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OCELLSIZE[4:0] This value indicates the minimum cell size and will be used to detect cell underrun errors. This
Register Bit(s)
ITESTDONE
OSHLBENB
OTESTENB
ITESTPASS
TRISTN
Used during the internal built-in self-test mode. Indicates that the single-ended versions of the
transmit module outputs should be looped back into the single-ended inputs of the receive
module.
OSHLENB = 0: No loopback.
OSHLENB = 1: Loopback.
value should be set and stable prior to initialization of operation and stable thereafter.
Enables the internal self-test of the RapidIO block. Two loopback paths exist during test, inter-
nal and external. During both tests, data is passed through all modules and verified.
Indicates the completion of the internal test. Only valid during a test when OTESTENB is high.
ITESTDONE = 0: Test running.
ITESTDONE = 1: Test complete.
Indicates the success of the internal test. This signal is valid only when ITESTDONE is high.
ITESTPASS = 0: Test failed.
ITESTPASS = 1: Test passed.
Active-low. 3-state override for transmit outputs. This signal is ignored during reset, but takes
priority over all 3-state control signals when active.
(continued)
Description
Agere Systems Inc.
August 2001
Data Sheet