ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 68

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Pin Information
Table 30. FPSC Function Pin Description (continued)
* The V
68
HSI Test Signals
RapidIO LVDS Interface Pins (Receiver)
lvctap_a<1:0>
lvctap_b<4:0>
rxd_a_p<7:0>
rxd_a_n<7:0>
rxd_b_p<7:0>
rxd_b_n<7:0>
lvctap_c<4:0>
rxd_c_p<7:0>
rxd_c_n<7:0>
tstMUX[9:0]s
SS
scan_tstmd
V
V
rxsoc_a_p
rxsoc_a_n
rxsoc_b_p
rxsoc_b_n
rxsoc_c_p
rxsoc_c_n
rxclk_a_p
rxclk_a_n
rxclk_b_p
rxclk_b_n
rxclk_c_p
rxclk_c_n
A_shim is combimed with V
scan_en
e_toggle
DD
SS
Symbol
tstsuftld
exdnup
mreset
resettx
testrst
tstclk
ref10
ref14
reshi
reslo
elsel
A_shim
A_shim
(continued)
I/O
—
—
—
—
—
—
—
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SS
in packages that contain an internal V
Test clock for emulation of 622 MHz clock during PLL bypass. Internal pull-down.
Test mode reset. Internal pull-down.
Resets receiver clock division counter. Internal pull-up.
Resets transmitter clock division counter. Internal pull-up.
Test mode output port.
Test mode enable. Must be tie-low for normal operation.
Scan test enable. Internal pull-up.
Internal pull-down.
Internal pull-down.
Internal pull-down.
Internal pull-down.
LVDS data for RapidIO, receiver port A.
LVDS data for RapidIO, receiver port A.
LVDS start-of-cell for RapidIO, receiver port A.
LVDS start-of-cell for RapidIO, receiver port A.
LVDS receive clock for RapidIO, receiver port A.
LVDS receive clock for RapidIO, receiver port A.
LVDS input center tap (use 0.01 uF to GND) internal pull-up.
LVDS data for RapidIO, receiver port B.
LVDS data for RapidIO, receiver port B.
LVDS start-of-cell for RapidIO, receiver port B.
LVDS start-of-cell for RapidIO, receiver port B.
LVDS receive clock for RapidIO, receiver port B.
LVDS receive clock for RapidIO, receiver port B.
LVDS input center tap (use 0.01 µF to GND) internal pull-up.
LVDS data for RapidIO, receiver port C.
LVDS data for RapidIO, receiver port C.
LVDS start-of-cell for RapidIO, receiver port C.
LVDS start-of-cell for RapidIO, receiver port C.
LVDS receive clock for RapidIO, receiver port C.
LVDS receive clock for RapidIO, receiver port C.
LVDS input center tap (use 0.01 µF to GND) internal pull-up.
LVDS reference voltage: 1.0 V ± 3%.
LVDS reference voltage: 1.4 V ± 3%.
LVDS resistor high pin ( 100
LVDS resistor low pin ( 100
Analog V
Analog V
DD
SS
for the Rapid IO block.
1.5 V power supply for the Rapid IO block.
SS
in series with reshi).
in series with reslo).
plane.
Description
Agere Systems Inc.
August 2001
Data Sheet