PAC-POWR1208 LATTICE [Lattice Semiconductor], PAC-POWR1208 Datasheet

no-image

PAC-POWR1208

Manufacturer Part Number
PAC-POWR1208
Description
ispPAC-POWR1208 Evaluation Board
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
ispPAC-POWR1208 Evaluation Board
PAC-POWR1208-EV
April 2004
Application Note AN6040
Introduction
®
The Lattice Semiconductor ispPAC
-POWR1208 In-System-Programmable Analog Circuit allows designers to
implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a
single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET
drivers with the digital functionality of a Programmable Logic Device (PLD), the ispPAC-POWR1208 provides the
power-supply designer with a rich set of features in a single device.
ISP™ (In-System-Programmability) provides the designer with an unprecedented level of flexibility, allowing him to
configure analog parameters such as threshold voltages as well as defining state machines and combinatorial logic
2
®
functions. All configuration data is stored internally in E
CMOS
nonvolatile memory. Programming a configuration
is accomplished through an industry-standard JTAG IEEE 1149.1 interface.
PAC-POWR1208-EV Evaluation Board
The PAC-POWR1208-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the isp-
PAC-POWR1208 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP pack-
age, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user
®
prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD
programming cable con-
nected between the evaluation board and a PC’s parallel (printer) port. Both analog and digital features of the isp-
®
PAC-POWR1208 can be easily configured using PAC-Designer
software.
Figure 1. PAC-POWR1208-EV Evaluation Board
www.latticesemi.com
1
an6040_01

Related parts for PAC-POWR1208

PAC-POWR1208 Summary of contents

Page 1

... JTAG IEEE 1149.1 interface. PAC-POWR1208-EV Evaluation Board The PAC-POWR1208-EV evaluation board (Figure 1) allows the designer to quickly configure and evaluate the isp- PAC-POWR1208 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP pack- age, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user prototyping. JTAG programming signals can be generated by using an ispDOWNLOAD nected between the evaluation board and a PC’ ...

Page 2

... Power Supply Considerations The ispPAC-POWR1208 operates with power supplies ranging from 2.25V to 5.5V, and allows for separate core (VDD) and I/O (VDDINP) voltages. Voltages ranging from 0 to 5.75V may be monitored at any of the 12 VMONx pins independent of the values of VDD and VDDINP. For device programming, however, VDD MUST be set to 3.3V. ...

Page 3

... JTAG interface header (P2) to allow for connecting multiple PAC-POWR1208-EV evaluation boards into a multi-device programming chain. Access to the ispPAC-POWR1208’s I/O pins is available at P5, which is a 2x20 row of pads to which one may attach test probes or a ribbon-cable connector. At this point all of the device’s I/O pins (except those required for the JTAG programming interface) are accessible ...

Page 4

... JTAG TDO line, and will flash when a download is being performed. Additionally, four LEDs are attached to the ispPAC-POWR1208’s OUT5-OUT8 lines. By adding appropriate code to the sequencer program, these LEDs can be made to indicate the internal status of the ispPAC-POWR1208, and can be a useful debug aid. ...

Page 5

... Lattice Semiconductor Figure 5. Top-side Foil Figure 6. Bottom-side Foil PAC-POWR1208-EV 5 ...

Page 6

... T-1-3/4 red LED 1x8 header strip, single row, 0.1” spacing Red banana jack Black banana jack 470 ohm SIP-8 resnet, 7-resistor SIP, bussed type 10K resistor 2K 5% resistor Pushbutton switch T1-3/4 green LED ispPAC-POWR1208 6 PAC-POWR1208-EV ...

Related keywords