NT5TU64M16DG-AC Nanya Technology, NT5TU64M16DG-AC Datasheet
NT5TU64M16DG-AC
Manufacturer Part Number
NT5TU64M16DG-AC
Description
Manufacturer
Nanya Technology
Datasheet
1.NT5TU64M16DG-AC.pdf
(79 pages)
Specifications of NT5TU64M16DG-AC
Case
BGA
Date_code
10+
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NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG
1Gb DDR2 SDRAM
Features
CAS Latency and Frequency
Description
The 1Gb Double-Data-Rate-2 (DDR2) DRAMs is a high-
speed CMOS Double Data Rate 2 SDRAM containing
1,073,741,824 bits. It is internally configured as an octal-bank
DRAM.
The 1Gb chip is organized as either 32Mbit x 4 I/O x 8 bank,
16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device.
These synchronous devices achieve high speed double-data-
rate transfer rates of up to 800 Mb/sec/pin for general appli-
cations.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength data-
output driver, (4) variable data-output impedance adjustment
and (5) an ODT (On-Die Termination) function.
REV 1.2
05/2008
Speed Sorts
Bin
max. Clock
Frequency
Data Rate
CAS Latency
t
t
t
RCD
RP
RC
• 1.8V ± 0.1V Power Supply Voltage
• 8 internal memory banks
• Programmable CAS Latency:
• Programmable Additive Latency: 0, 1, 2, 3, 4 and 5
• Write Latency = Read Latency -1
• Programmable Burst Length: 4 and 8
• Programmable Sequential / Interleave Burst
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• 4 bit prefetch architecture
• Data-Strobes: Bidirectional, Differential
(CL-tRCD-TRP)
3, 4, 5(DDR2/533/667/800-CL5)
4,5,6 (DDR2-800-CL6)
-37B/-37BI
DDR2-533
4-4-4
266
533
15
15
60
4
DDR2-667
-3C/-3CI
5-5-5
333
667
15
15
60
5
DDR2-800
1
-AD/-ADI
6-6-6
400
800
15
15
60
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS pair in a source synchronous fash-
ion. A 14 bit address bus for x4 and x8 organised compo-
nents and a 13 bit address bus for x16 component is used to
convey row, column, and bank address devices.
These devices operate with a single 1.8V +/- 0.1V power sup-
ply and are available in BGA packages.
6
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
• Industrial grade device supports -40
• 1KB page size for x 4 & x 8,
• Strong and Weak Strength Data-Output Driver
• Auto-Refresh and Self-Refresh
• Power Saving Power-Down modes
• 7.8 µs max. Average Periodic Refresh Interval
• RoHS Compliance
•
temperature (-37BI/-3CI/-ADI/-ACI)
2KB page size for x16
Packages:
60-Ball BGA for x4 / x8 components
84-Ball BGA for x16 components
DDR2-800
-AC/-ACI
5-5-5
12.5
12.5
57.5
400
800
5
©
NANYA TECHNOLOGY CORP
Mb/s/pin
Units
MHz
tck
tck
ns
ns
ns
o
C~95
. All rights reserved.
o
C operating
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