K7R641884M SAMSUNG [Samsung semiconductor], K7R641884M Datasheet - Page 2

• Manufacturer Part Number: K7R641884M
• Description: 2Mx36 & 4Mx18 QDRTM II b4 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

FUNCTIONAL BLOCK DIAGRAM
K7R643684M
FEATURES
K7R641884M
D(Data in)
ADDRESS
R
W
BW
K
K
C
C
2Mx36-bit, 4Mx18-bit QDR
• 1.8V+0.1V/-0.1V Power Supply.
• DLL circuitry for wide output data valid window and future
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
• Separate independent read and write data ports
• HSTL I/O
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed late write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 4-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two input clocks(K and K) for accurate DDR timing at clock
• Two input clocks for output data(C and C) to minimize
• Two echo clocks (CQ and CQ) to enhance output data
• Single address bus.
• Byte write function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 15x17mm
Notes: 1. Numbers in ( ) are for x18 device.
with concurrent read and write operation
freguency scaling.
1.8V+0.1V/-0.1V for 1.8V I/O
rising edges only.
clock-skew and flight-time mismatches.
traceability.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.
X
4 (or 2)
36 (or 18)
19 (or 20)
LOGIC
DATA
CTRL
REG
ADD
REG
GEN
CLK
(or 20)
19
TM
SELECT OUTPUT CONTROL
II b4 SRAM
72(or 36)
WRITE DRIVER
MEMORY
(4Mx18)
ARRAY
2Mx36
- 2 -
2Mx36 & 4Mx18 QDR
Organization
72(or 36)
X36
X18
(or 36)
(or 36)
72
72
K7R643684M-FC30
K7R643684M-FC25
K7R643684M-FC20
K7R643684M-FC16
K7R641884M-FC30
K7R641884M-FC25
K7R641884M-FC20
K7R641884M-FC16
Number
Part
(or 72)
144
TM
Cycle
Time
3.3
4.0
5.0
6.0
3.3
4.0
5.0
6.0
Preliminary
II b4 SRAM
(Echo Clock out)
Access
Time
36 (or 18)
0.45
0.45
0.45
0.50
0.45
0.45
0.45
0.50
Q(Data Out)
CQ, CQ
Oct. 2004
Rev 0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns