H5PS5162FFR-C HYNIX [Hynix Semiconductor], H5PS5162FFR-C Datasheet - Page 16

• Manufacturer Part Number: H5PS5162FFR-C
• Description: 512Mb DDR2 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.0 / July. 2008
IDD7
Note:
1. VDDQ = 1.8 +/- 0.1V ; VDD = 1.8 +/- 0.1V
2. IDD specifications are tested after the device is properly initialized
3. Input slew rate is specified by AC Parametric Test Condition
4. IDD parameters are specified with ODT disabled.
5. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
6. Definitions for IDD
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks)
for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals not including masks or strobes.
(exclusively VDDQ = 1.9 +/- 0.1V ; VDD = 1.9 +/- 0.1V for C3 speed grade)
with all combinations of EMRS bits 10 and 11.
LOW is defined as Vin £ VILAC(max)
HIGH is defined as Vin Š VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL
= CL(IDD), AL = t RCD(IDD)-1* t CK(IDD); t CK = t CK(IDD), t RC = t RC(IDD), t RRD = t RRD(IDD),
t RCD = 1* t CK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for
detailed timing conditions
H5PS5162FFR series
Release
mA
16