XCB56364PV100 MOTOROLA [Motorola, Inc], XCB56364PV100 Datasheet - Page 38
XCB56364PV100
Manufacturer Part Number
XCB56364PV100
Description
24-Bit Audio Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.XCB56364PV100.pdf
(162 pages)
- Current page: 38 of 162
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Specifications
External Memory Expansion Port (Port A)
2-18
Notes:
No.
113
114
115
116
117
118
119
RD deassertion time
WR deassertion time
Address valid to RD assertion
RD assertion pulse width
RD deassertion to address not
valid
TA setup before RD or WR
deassertion
TA hold after RD or WR deasser-
tion
1.
2.
3.
4.
WS is the number of wait states specified in the BCR.
Timings 100, 107 are guaranteed by design, not tested.
All timings for 100 MHz are measured from 0.5
In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to
remain active
Characteristics
Table 2-8 SRAM Read and Write Accesses
4
Freescale Semiconductor, Inc.
For More Information On This Product,
DSP56364 Advance Information
Go to: www.freescale.com
Symbol
·
Vcc to .05
(WS + 0.25)
0.25
0.75
1.75
2.75
0.25
1.25
2.25
0.5
2.5
3.5
0.5
Expression
[1
[4
[2
[4
[1
[4
[WS = 1]
[WS
[WS
[WS
T
C
WS
WS
WS
WS
WS
WS
·
T
T
T
T
T
T
T
T
T
T
T
C
C
C
C
Vcc
C
C
C
C
C
C
2.0
C
3
8]
8]
8]
+ 2.0
T
(continued)
4.0
4.0
4.0
4.0
3]
7]
3]
7]
3]
7]
4.0
4.0
4.0
2.0
2.0
C
1
.0
4.0
13.5
23.5
21.0
31.0
10.5
20.5
Min
3.5
1.0
6.0
1.0
8.5
0.5
4.5
0
Max
MOTOROLA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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