XCB56364PV100 MOTOROLA [Motorola, Inc], XCB56364PV100 Datasheet - Page 74

• Manufacturer Part Number: XCB56364PV100
• Description: 24-Bit Audio Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

Specifications
Serial Host Interface (SHI) I
2.12.1
The programmed serial clock cycle, T
HCKR (SHI clock control register).
The expression for T
2-54
No.
186 First SCL sampling edge to
187 Last SCL edge to HREQ out-
188 HREQ in assertion to first SCL
HREQ output deassertion
put not deasserted
edge
where
— HRS is the prescaler rate select bit. When HRS is cleared, the fixed
— HDM[7:0] are the divider modulus select bits.
— A divide ratio from 1 to 64 (HDM[5:0] = 0 to $3F) may be selected.
Programming the Serial Clock
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
Characteristics
Narrow filters enabled 2
Narrow filters enabled
Narrow filters enabled
Wide filters enabled
Wide filters enabled
Wide filters enabled
Filters bypassed
Filters bypassed
Filters bypassed
I
2
CCP
Table 2-18 SHI I
2
T
I
is
2
CCP
Freescale Semiconductor, Inc.
For More Information On This Product,
2
= [T
2
C Protocol Timing
C
DSP56364 Advance Information
I
2
0.5
CCP
2
0.5
Go to: www.freescale.com
2
2
Expression
2
2
2
Symbol/
T
T
T
NG;RQO
AS;RQO
, is specified by the value of the HDM[5:0] and HRS bits of the
T
T
T
AS;RQI
(HDM[7:0] + 1)
T
T
T
R
2
T
C
C
C
T
C
C
C
C Protocol Timing (continued)
P
Standard I
I
+ 120
+ 208
+ 135
2
C
+ 30
+ 30
+ 80
(min) = 1.5 k¾
CCP
- 21
-
Standard-Mode
4327
4282
4238
Min
100
155
2
50
—
—
—
C*
(7
Max
(1 – HRS) + 1)]
140
228
50
—
—
—
—
—
—
Min
100
155
927
882
838
Fast-Mode
50
—
—
—
MOTOROLA
Max
140
228
50
—
—
—
—
—
—
Unit
ns
ns
ns