K9K1208Q0C Samsung semiconductor, K9K1208Q0C Datasheet - Page 27

• Manufacturer Part Number: K9K1208Q0C
• Description: 64M x 8 Bit / 32M x 16 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

DEVICE OPERATION
PAGE READ
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-
ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera-
tion. Two types of operations are available : random read, serial page read.
The random read mode is enabled when the page address is changed. The 528 bytes(X8 device) or 264 words(X16 device) of data
within the selected page are transferred to the data registers in less than 10µs(t
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in
50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data starting from the selected column
address up to the last column address[column 511/ 527(X8 device) 255 /263(X16 device) depending on the state of GND input pin].
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512
~527 bytes(X8 device) or 256~263 words(X16 device) may be selectively accessed by writing the Read2 command with GND input
pin low. Addresses A
ignored in X8 device case or A
main area. Figures 8, 9 show typical sequence and timings for each read operation.
Figure 8. Read1 Operation
K9K1208Q0C
K9K1208D0C
K9K1208U0C
NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half
CLE
CE
WE
ALE
R/B
RE
I/Ox
array (00h) at next cycle.
00h
X16 device : A
X8 device : A
0~
A
3
Start Add.(4Cycle)
(X8 device) or A
K9K1216Q0C
K9K1216D0C
K9K1216U0C
3~
0
A
0
~ A
~ A
7
must be "L" in X16 device case. The Read1 command is needed to move the pointer back to the
7
7
& A
& A
01h command is only available on X8 device(K9K1208X0C).
9
9
~ A
~ A
0~
A
25
25
2
(X16 device) set the starting address of the spare area while addresses A
t
R
(00h Command)
Data Field
Main array
27
Spare Field
R
). The system controller can detect the completion of
Data Output(Sequential)
1)
1st half array
FLASH MEMORY
(01h Command)
Data Field
2st half array
Spare Field
4
~A
7
are