HY5DU561622ELFP-D43 HYNIX [Hynix Semiconductor], HY5DU561622ELFP-D43 Datasheet - Page 28
HY5DU561622ELFP-D43
Manufacturer Part Number
HY5DU561622ELFP-D43
Description
256Mb DDR SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.HY5DU561622ELFP-D43.pdf
(29 pages)
- Current page: 28 of 29
- Download datasheet (254Kb)
Rev. 1.1 / June 2006
CAPACITANCE
Note:
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Input Clock Capacitance
Delta Input Clock Capacitance
Input Capacitance
Delta Input Capacitance
Input / Output Capacitance
Delta Input / Output Capacitance
Parameter
(T
Output
A
=25
o
C, f=100MHz)
CK, /CK
CK, /CK
All other input-only pins
All other input-only pins
DQ, DQS, DM
DQ, DQS, DM
O
DC = VDDQ/2, V
Zo=50Ω
C
R
L
=30pF
T
Pin
=50Ω
O
V
peak-to-peak = 0.2V
TT
V
REF
Delta C
Delta C
Delta C
Symbol
C
C
C
IO
I1
I1
IO
I1
I2
HY5DU561622E(L)FP
HY5DU56822E(L)FP
Min
2.0
2.0
4.0
-
-
-
Max
0.25
3.0
3.0
0.5
5.0
0.5
Unit
pF
pF
pF
pF
pF
pF
28
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