LS7166_06 LSI [LSI Computer Systems], LS7166_06 Datasheet

LS7166_06

Manufacturer Part Number

LS7166_06

Description

24-BIT QUADRATURE COUNTER

Manufacturer

LSI [LSI Computer Systems]

Datasheet

1.LS7166_06.pdf (15 pages)

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7166-082906-1

FEATURES:

• Programmable modes are: Up/Down,

• DC to 25MHz Count Frequency.

• 8-Bit I/O Bus for uP Communication and Control.

• 24-Bit comparator for pre-set count comparison.

• Readable status register.

• Input/Output TTL and CMOS compatible.

• 3V to 5.5V operation (V

• LS7166 (DIP); LS7166-S (SOIC);

GENERAL DESCRIPTION:

The LS7166 is a CMOS, 24-bit counter that can be pro-

grammed to operate in several different modes. The oper-

ating mode is set up by writing control words into internal

control registers (see Figure 8). There are three 6-bit and

one 2-bit control registers for setting up the circuit functional

characteristics. In addition to the control registers, there is a

5-bit output status register (OSR) that indicates the current

counter status. The IC communicates with external circuits

through an 8-bit three state I/O bus. Control and data words

are written into the LS7166 through the bus. In addition to

the I/O bus, there are a number of discrete inputs and out-

puts to facilitate instantaneous hardware based control func-

tions and instantaneous status indication.

Internal hardware registers are accessible through the I/O

bus (D0 - D7) for READ or WRITE when CS = 0. The C/D in-

put selects between the control registers (C/D = 1) and the

data registers (C/D = 0) during a READ or WRITE operation.

(See Table 1)

Binary, BCD, 24 Hour Clock, Divide-by-N,

x1 or x2 or x4 Quadrature and Single-Cycle.

LS7166-TS24 (24-Pin TSSOP) - See Figure 1 -

U L

A3800

LSI/CSI

The information included herein is believed to be

accurate and reliable. However, LSI Computer Systems,

Inc. assumes no responsibilities for inaccuracies, nor for

any infringements of patent rights of others which may

result from its use.

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

- V

24-BIT QUADRATURE COUNTER

LCTR/LLTC

ABGT/RCTR

LCTR/LLTC

PIN ASSIGNMENTS - Top View

( +V)

(631) 271-0400 FAX (631) 271-0405

LS7166

DIP and SOIC

FIGURE 1

20-PIN

2 4 - P I N

TSSOP

August 2006

C/D

( -V )

( - V )

( +V)

Related parts for LS7166_06

LS7166_06 Summary of contents

Page 1

LSI/CSI U L ® LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 A3800 FEATURES: • Programmable modes are: Up/Down, Binary, BCD, 24 Hour Clock, Divide-by- Quadrature and Single-Cycle. • 25MHz ...

Page 2

PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a 24 bit data via the PR. The data is first written into the WRITE cycle sequence of Byte 0 ...

Page 3

TABLE 1 - Register Addressing Modes ...

Page 4

OCCR (Output Control Register) Initializes CNTR and output operating modes. Bit # (Quadrature Register). Selects quadrature count mode (See Fig. 7) Bit # ...

Page 5

I/O DESCRIPTION: (See REGISTER DESCRIPTION for I/O Prgramming.) Data-Bus (D0 - D7) (Pin 8 - Pin 15). The 8-line data bus is a three-state I/O bus for interfacing with the system bus. CS (Chip Select Input) (Pin 2). A logical ...

Page 6

TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig 5.5V 0˚ to 85˚C, unless otherwise specified Parameter Clock A/B "Low” Clock A/B "High" Clock A/B Frequency (See NOTE 1) Clock ...

Page 7

LTCR CLK ( CLK (B) Q0 (Internal) Q1 (Internal) Q2-Q23 (Internal) CNTR=FFFFFD CNTR=FFFFFE CNTR=FFFFFF CNTR=000000 (PR=CNTR) COMP NOTE FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW ...

Page 8

T SRS CS C/D T CRS DATA BUS VALID OUTPUT CS C/D WR DATA BUS LCTR DN CLK Q0 (INTERNAL) Q1 (INTERNAL) Q2-Q23 (INTERNAL) CNTR LD (INTERNAL) BW CNTR LOAD (LCTR or MCR BASED) UP CLK OR ...

Page 9

A B UPCLK (x1) (Internal) DNCLK (x1) (Internal) UPCLK (x2) (Internal) DNCLK (x2) (Internal) UPCLK (x4) (Internal) DNCLK (x4) (Internal) UP/DN (OSR Bit 7166-110503-9 FORWARD CQV T CQV T CBW FIGURE 7. ...

Page 10

SELECT INPUT (READ INPUT) RD (WRITE INPUT (CONTROL /DATA INPUT) C/D 6 (COUNT INPUT (COUNT INPUT (AB GATE/LOAD LATCH) ABGT/RCTR (LOAD CTR/LOAD LATCH) LCTR/LLTC 3 PR/OL ADDRESS ...

Page 11

FIGURE 9. 80C31/8051 TO LS7166 INTERFACE IN EXTERNAL ADDRESS MODE 8051 80C31 AD0 P0.0 AD1 P0.1 AD2 P0.2 AD3 P0.3 AD4 P0.4 AD5 P0.5 AD6 P0.6 AD7 P0.7 ALE WR/ RD/ NOTE: Port_0 is open drain output. Add pull-up resistors ...

Page 12

FIGURE 10. 8751 INTERFACE TO LS7166 IN I/O MODE UR 31 VCC P0.0 ER/VP P0.1 P0 P0.3 P0.4 18 P0.5 X2 P0.6 9 P0.7 RESET P2.0 12 INT0 P2.1 13 8051 P2.2 INT1 15 T0 P2.3 14 P2.4 ...

Page 13

U1 XTAL 30 PA3 5 EXTAL 29 PA4 4 PA5 3 39 RESET PA6 2 41 IRQ PA7 1 40 XIRD 8 PA0 16 PB0 7 PA1 15 PB1 6 PA2 14 PB2 13 17 PE0 PB3 12 18 PE1 ...

Page 14

ISA BUS AEN IOR/ IOW/ 7166-110503-14 FIGURE 12. LS7166 INTERFACE EXAMPLE ADDRESS DECODER LS7166 8 ...

Page 15

FIGURE 13. 68000 INTERFACE TO LS7166 ADDRESS R/W LDS/UDS 68000 68008 68010 AS DTACK CLK CLOCK 7166-062306-15 DATA BUS LS373 DECODE S74 S74 ...

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