IW4029 INTEGRAL [Integral Corp.], IW4029 Datasheet
IW4029
Related parts for IW4029
IW4029 Summary of contents
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... TECHNICAL DATA Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS The IW4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consists CARRY IN,(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT signal are provided as outputs ...
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... For proper operation, V GND ( OUT CC Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V Unused outputs must be left open. Parameter SOIC Package+ Parameter and V IN IW4029B Value Unit -0.5 to + ...
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... IW4029B DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage V Maximum Low -Level IL Input Voltage V Minimum High-Level OH Output Voltage V Maximum Low-Level OL Output Voltage I Maximum Input IN Leakage Current I Maximum Quiescent CC Supply Current (per Package) I Minimum Output Low OL (Sink) Current I Minimum Output OH High (Source) Current ...
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... FUNCTION TABLE LOGIC LEVEL H BINARY COUNT L DECADE COUNT COUNTER ADVANCE AT POS. CLOCK TRANSITION L ADVANCE COUNTER AT POS. CLOCK TRANSITION IW4029B =t =20 ns Guaranteed Limit Unit 25 C 125 MHz 4 2 5.5 2.75 500 1000 ns 240 480 180 360 ...
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... IW4029B TIMING REQUIREMENTS Symbol Parameter t Minimum Pulse Width, Clock (Figure Minimum Pulse Width, Preset Enable w (Figure Minimum Setup Time, Clock to B/D or U/D su (Figure Minimum Removal Time, Preset Enable (Figure rem Minimum Hold Time, Clock to Carry In (Figure Minimum Setup Time, Carry In to Clock ...
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... Figure 1. Switching Waveforms Figure 2. Switching Waveforms IW4029B 69 ...
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... IW4029B TIMING DIAGRAM; binary mode; J1=HIGH; J2=LOW; BIN/DEC=HIGH TIMING DIAGRAM; decade mode; J1=LOW; J4=LOW; BIN/DEC=LOW 70 ...
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... IW4029B EXPANDED LOGIC DIAGRAM TRUTH TABLE CLOCK ...