IW4029 INTEGRAL [Integral Corp.], IW4029 Datasheet - Page 5

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IW4029

Manufacturer Part Number
IW4029
Description
Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS
Manufacturer
INTEGRAL [Integral Corp.]
Datasheet
IW4029B
TIMING REQUIREMENTS
*
**
68
From Up/Down, Binary/Decode, Carry In, or Preset Enable Control Inputs to Clock Edge.
Symbol
From Carry In to Clock Edge
t
t
r
t
t
, t
rem
t
t
t
h
su
su
w
w
**
f
*
**
*
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Preset Enable
(Figure 1)
Minimum Setup Time, Clock to B/D or U/D
(Figure 1)
Minimum Removal Time, Preset Enable (Figure
1)
Minimum Hold Time, Clock to Carry In (Figure
2)
Minimum Setup Time, Carry In to Clock
(Figure 1)
Maximum Input Rise and Fall Times,Clock
(Figure 2)
Parameter
(C
L
=50pF, R
L
=200 k , Input t
V
5.0
5.0
5.0
5.0
5.0
5.0
5.0
10
15
10
15
10
15
10
15
10
15
10
15
10
15
V
CC
r
=t
f
=20 ns)
-55 C
180
130
340
140
100
200
110
200
90
60
70
50
80
50
30
25
70
60
15
15
15
Guaranteed Limit
25 C
180
130
340
140
100
200
110
200
90
60
70
50
80
50
30
25
70
60
15
15
15
125 C
360
180
120
260
140
100
680
280
200
400
220
160
100
400
140
120
60
50
30
30
30
Unit
ns
ns
ns
ns
ns
ns
s

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