BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 104

• Manufacturer Part Number: BT8375
• Description: single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
• Manufacturer: CONEXANT [Conexant Systems, Inc]

2.0 Circuit Description
2.9 Transmit Line Interface Unit
2.9.2 Transmit Phase Lock Loop
Figure 2-40. TPLL Input Clock Jitter Tolerance
2-76
2.9.2.1 Clock Reference
100.0
1.0 k
10.0
10 k
1.0
0.1
0.1
138 UI
1.0
The Transmit Phase Lock Loop (TPLL) operates at a nominal rate of either 1.544
MHz or 2.048 MHz, selected by T1/E1N [CR0; addr 001]. The pull-in and
hold-in range of the TPLL is 200 ppm. The TPLL produces the transmit clock
(TCKO) and an 8x clock that is used by the pulse shape block to generate the
AMI pulses from TCKI clock mux, or JCLK.
The TPLL reference clock is provided on the TCKO pin. If the jitter attenuator is
enabled in the transmit direction [JDIR; addr 002], TCKO is the dejittered TCKI
clock, or JCLK (if CLAD is enabled); otherwise, TCKO equals TCKI. The TCKI
source is selected by TCKI[1:0] [CMUX; addr 01A]. TCKI can have the
following selections: Recovered Receive Clock (RCKO), Receive System Bus
Clock Input (RSBCKI), Clock Rate Adapter Output (CLADO), or an external
clock, which is provided on the TCKI pin. The input clock jitter tolerance of the
TPLL is illustrated in
Sine Wave Jitter Frequency (Hz) [Log Scale]
10.0
TR 62411
28 UI
Conexant
Figure
100.0
2-40.
Fully Integrated T1/E1 Framer and Line Interface
1.0 k
TPLL
40 dB/Decade
10.0 k
0.2 UI
Bt8370/8375/8376
100.0 k
2 UI
N8370DSE