BT8375 CONEXANT [Conexant Systems, Inc], BT8375 Datasheet - Page 133
BT8375
Manufacturer Part Number
BT8375
Description
single chip transceivers for T1/E1 and Integrated Service Digital Network (ISDN) primary rate interfaces
Manufacturer
CONEXANT [Conexant Systems, Inc]
Datasheet
1.BT8375.pdf
(323 pages)
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Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.4 Interrupt Status Registers
Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no
effect.
reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt
enable is active (high), each interrupt event forces the associated IRR bit active (high) and the INTR* output pin
active (low). Interrupt sources fall into two categories:
Otherwise, the interrupt status is latched and reported according to the selected latching mode [LATCH;
addr 046] without asserting the INTR* output pin.
Table 3-3. Interrupt Status Register Summary
N8370DSE
NOTE(S):
(1)
Bit
An Interrupt Status register (ISR) bit is latched active (high) whenever its corresponding interrupt source
Interrupt events are reported in real time on the INTR* output pin if the interrupt enable is active (high).
0
1
2
3
4
5
6
7
These bits are not active in the Bt8376 Device.
• Rising-edge source reports an interrupt event when status changes from inactive to active state. Unless
• Dual-edge source reports an interrupt event when status changes from inactive to active (rising edge),
specifically noted otherwise, all ISR bits are rising-edge sources.
or from active to inactive (falling edge). The processor must read the associated real-time status to
determine which edge occurred.
ALARM1
SIGFRZ
RMYEL
RALOS
RLOS
RPDV
RLOF
RYEL
ISR7
RAIS
004
ALARM2
LOOPUP
LOOPDN
ONESEC
TSHORT
TLOC
TPDV
ISR6
TLOF
005
—
ERROR
CKERR
MERR
RSLIP
TSLIP
SERR
CERR
FERR
JERR
ISR5
006
FERR[12]
BERR[12]
FEBE[10]
CRC[10]
COFA[2]
RLOF[4]
LCV[16]
COUNT
SEF[2]
Conexant
ISR4
Table 3-3
007
summarizes the interrupt status registers.
RMSYNC
TMSYNC
RFRAME
TFRAME
TIMER
ISR3
RSIG
TSIG
RMF
TMF
008
TEMPTY
TDLERR
RNEAR
TNEAR
RFULL
TMSG
RMSG
TBOP
ISR2
DL1
009
3.4 Interrupt Status Registers
TEMPTY
TDLERR
TNEAR
RNEAR
RFULL
RMSG
TMSG
RBOP
ISR1
00A
DL2
(1)
(1)
(1)
(1)
(1)
(1)
(1)
3.0 Registers
TMERR
TSERR
TCERR
PSYNC
TFERR
BSLIP
PATT
ISR0
00B
—
—
3-15
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