PM7325-TC PMC [PMC-Sierra, Inc], PM7325-TC Datasheet

PM7325-TC

Manufacturer Part Number

PM7325-TC

Description

S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet Preliminary

Manufacturer

PMC [PMC-Sierra, Inc]

Datasheet

1.PM7325-TC.pdf (2 pages)

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FEATURES

• Monolithic single chip device which

• Instantaneous transfer rate of 3200

• Can be configured as an Ingress mode

• POS-PHY/UTOPIA Level 3 PHY and

• Supports a full duplex 16 bit 5 2MHz

PMC-1990444 (p2)

BLOCK DIAGRAM

2.4 Gbit/s ATM Layer Solution

handles ATM Layer functions for one

direction including VPI/VCI address

translation, cell appending, cell rate

policing, cell counting and OAM

requirements for 64 k VCs (virtual

connections). Two or more PM7325

S/UNI

cascaded to support additional VC's.

Mbit/s supports a cell transfer rate of

5.68x10

device or an Egress mode device.

Switch interface supports a 32-bit

104 MHz interface. Extended cell

format is supported (52 - 64 byte cell).

Packets are not processed and are

buffered and passed through

transparently. Handles up to 48 logical

PHY ports.

SCI-PHY™ Backwards Cell Interface

Port which allows an Ingress mode

device and an Egress mode device to

communicate and behave as a single

bi-directional device.

-ATLAS-3200 devices can be

cells/s.

PMC-Sierra,Inc.

PROPRIETARY AND CONFIDENTIAL TO PMC - SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Cell Flow

ICIF

SCI-PHY Rx Master

Interface

IBCIF

• Supports a 64-bit (with or without

• Includes a FIFO buffered 32-bit

• Per-PHY output buffering scheme

• Ingress and Egress functions include

POLICING

• ITU-I.371, ATM Forum TM4.1

• Per-PHY single leaky-bucket policing

parity) 125 MHz External Pipelined

ZBT SRAM interface.

microprocessor bus interface for cell

insertion and extraction, deterministic

VC Table access, status monitoring

and configuration of the device.

resolves the head-of-line blocking

issue.

flexible search engines that cover the

entire PHYID/VPI/VCI address range,

dual leaky-bucket policing, per-VC cell

counts, OAM-FM and OAM-PM

processing.

compliant, per-VC programmable dual

leaky-bucket policing with a

programmable action (tag, discard, or

count only) for each bucket, each with

three programmable 16 bit non-

compliant cell counts.

with a programmable action (tag,

discard, or count only).

Packet Bypass

SDQ

Microprocessor Interface

Cell Processor

125 MHz Pipelined ZBT

Policing, OAM,

MPIF

Translation

Preliminary

Statistics,

VC Table

(EDRAM)

SRAM Interface

SCI-PHY Rx Slave

JTAG Interface

• Guaranteed Frame Rate (GFR)

OAM

• ITU-I.610 (1999) compliant OAM on

• Complete Fault Management (AIS,

• Complete Performance Monitoring

• Per-PHY AIS/RDI generation.

CELL COUNTING

• Per-VC counts include CLP0 cells,

• Per-PHY counts include CLP0 cells,

• Per-device counts include total cells

Interface

OBCIF

Policing with Minimum Cell Rate

Frame Tagging.

both Ingress and Egress directions.

RDI, CC) processing, for VP/VC,

Segment/End-to-end flows on all VCs.

processing, for VP/VC, Segment/End-

to-end, Forward/Backward flows, on

512 Uni-directional VCs.

CLP1 cells, OAM cells, RM cells, and

invalid cells, cells violating the contract

and total AAL5 frames.

CLP1 cells, OAM cells, errored OAM

cells, unassigned/invalid cells and

policing violations.

received/transmitted, and physical

layer cells.

S/UNI®-ATLAS-3200

J T A G

OCIF

PM7325

Related parts for PM7325-TC

PM7325-TC Summary of contents

Page 1

... ATM Layer functions for one direction including VPI/VCI address translation, cell appending, cell rate policing, cell counting and OAM requirements for 64 k VCs (virtual connections). Two or more PM7325 ® S/UNI -ATLAS-3200 devices can be cascaded to support additional VC's. • Instantaneous transfer rate of 3200 ...

Page 2

... Canada Attn: Document Coordinator Tel: 604.415.6000 Fax: 604.415.6200 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE PM7325 S/UNI®-ATLAS-3200 Preliminary SRAM interface, and 3.3 V external interfaces (excluding the SRAM interface). • Packaged in a 768 pin Tape Ball Grid Array (TBGA) package ...

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