MX29LV640D MCNIX [Macronix International], MX29LV640D Datasheet - Page 18

• Manufacturer Part Number: MX29LV640D
• Description: 64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V
• Manufacturer: MCNIX [Macronix International]

MX29LV640D T/B
Customer Lockable: Security Sector NOT Programmed or Protected at the Factory
When the security feature is not required, the security region can act as an extra memory space.
Security silicon sector can also be protected by two methods. Note that once the security silicon sector is protected,
there is no way to unprotect the security silicon sector and the content of it can no longer be altered.
The first method is to write a three-cycle command of Enter Security Region, and then follow the sector group protect
algorithm as illustrated in Figure 14, except that RESET# pin may at either Vih or Vhv.
The other method is to write a three-cycle command of Enter Security Region, and then follow the alternate method of
sector protect with A9, OE# at Vhv.
After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a power
cycle, or issue a hardware reset to return the device to read normal array mode.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during
power up. Besides, only after successful completion of the specified command sets will the device begin its erase or
program operation.
Other features to protect the data from accidental alternation are described as followed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than Vlko. This prevents data from spuriously
altered. The device automatically resets itself when Vcc is lower than Vlko and write cycles are ignored until Vcc is
greater than Vlko. System must provide proper signals on control pins after Vcc is larger than Vlko to avoid uninten-
tional program or erase operation
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih,
WE# a Vih, or OE# at Vil.
POWER-UP SEQUENCE
Upon power up, MX29LV640D T/B is placed in read array mode. Furthermore, program or erase operation will begin
only after successful completion of specified command sequences.
P/N:PM1208
REV. 1.6, AUG. 16, 2008
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