DM9000_09 DAVICOM [Davicom Semiconductor, Inc.], DM9000_09 Datasheet - Page 7

• Manufacturer Part Number: DM9000_09
• Description: ISA to Ethernet MAC Controller with Integrated 10/100 PHY
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

5. Pin Description
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,
LI= reset Latch Input, #= asserted low
5.1 MII Interface
Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally
5.2 Processor Interface
Final
Version: DM9000-DS-F03
April 23, 2009
41,40,39,
53,52,51,
Pin No.
37
38
43
44
45
46
47
49
50
54
56
57
14
1
2
3
4
Pin Name
RXD [3:0]
TXD [3:0]
RX_CLK
TX_CLK
IOWAIT
TX_ EN
RX_DV
RX_ER
LINK_I
MDIO
IOW#
IOR#
MDC
CRS
COL
AEN
RST
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
External MII device link status
External MII Receive Data
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode
External MII Carrier Sense
Active high to indicate the pressure of carrier, due to receive or transmit activities
in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.
External MII Collision Detect. This pin is output in reverse MII interface.
External MII Receive Data Valid
External MII Receive Clock
External MII Transmit Clock. This pin in output in MII interface.
External MII Transmit Data
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps
nibble mode
TXD [2:0] is also used as the strap pins of IO base address.
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
External MII Transmit Enable
MII Serial Management Data
MII Serial Management Data Clock
This pin is also used as the strap pin of the polarity of the INT pin
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin
is high active
Processor Read Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Processor Write Command
This pin is low active at default, its polarity can be modified by EEPROM setting.
See the EEPROM content description for detail
Address Enable
A low active signal used to select the DM9000.
Processor Command Ready
When a command is issued before last command is completed, the IOWAIT will
be pulled low to indicate the current command is waited
External MII Receive Error
Hardware Reset Command, active high to reset the DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Description
DM9000
7