PM8611-BIAP PMC [PMC-Sierra, Inc], PM8611-BIAP Datasheet - Page 83

• Manufacturer Part Number: PM8611-BIAP
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010883, Issue 2
Register 007H: SBSLITE Receive Synchronization Delay
TIP
RC1FPDLY[13:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The transfer in progress bit (TIP) reports the status of latching performance monitor counting
into holding registers. TIP is set high when a transfer is initiated by a write access to the
SBSLITE Master Signal Monitor #1, Accumulation Trigger Register (014H). It is set low
when all the counters in the SBSLITE have transferred their values to holding registers. The
updated counts are now available for reading at the designated registers.
The receive transport frame delay bits (RC1FPDLY[13:0]) controls the delay, in SYSCLK
cycles, inserted by the SBSLITE before processing the C1 characters delivered by the receive
serial data links. RC1FPDLY should be set such that after the specified delay the active
receive link should have delivered the C1 character. The relationships between RC1FP,
RC1FPDLY and the receive serial links is described in the Functional Timing section.
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RC1FPDLY[13]
RC1FPDLY[12]
RC1FPDLY[11]
RC1FPDLY[10]
RC1FPDLY[9]
RC1FPDLY[8]
RC1FPDLY[7]
RC1FPDLY[6]
RC1FPDLY[5]
RC1FPDLY[4]
RC1FPDLY[3]
RC1FPDLY[2]
RC1FPDLY[1]
RC1FPDLY[0]
Function
TIP
Unused
SBSLITE™ Telecom Standard Product Data Sheet
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Preliminary
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