CH7008A-V ETC [List of Unclassifed Manufacturers], CH7008A-V Datasheet - Page 31
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CH7008A-V
Manufacturer Part Number
CH7008A-V
Description
Digital PC to TV Encoder Features
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
1.CH7008A-V.pdf
(49 pages)
- Current page: 31 of 49
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CHRONTEL
Register Descriptions (continued)
Video Bandwidth Register
This register enables the selection of alternative filters for use in the luma and chroma channels. There are currently
four filter options defined for the chroma channel, four filter options in the S-Video luma channel and two filter
options in the composite luma channel. The Tables 15 and 16 below show the various settings.
Bit 6 (CVBW) outputs the S-Video luma signal on both the S-Video luma output and the CVBS output. A 1 in this
location enables the output of a black and white image on composite video, thereby eliminating the degrading
effects of the color signal (such as dot crawl or false colors), which is useful for viewing text with high accuracy.
Bit 7 (FLFF) controls the flicker filter used in the 7/10’s scaling modes. In these scaling modes, setting FLFF to 1
causes a five line flicker filter to be used. The default setting of 0 uses a four line flicker filter.
201-0000-027 Rev 2.2, 9/30/99
Table 15. Luma Filter Bandwidth
Table 16. Chroma Filter Bandwidth
Bit:
Symbol:
Type:
Default:
YCV
0
1
YSV[1:0]
00
01
10
11
YPEAK
0
1
CBW[1:0]
0 0
0 1
1 0
1 1
7
FLFF
R/W
0
Luma Composite Video Filter Adjust
Low bandwidth
High bandwidth
Low bandwidth
Medium bandwidth
High bandwidth
Reserved
Disables the Y-peaking circuit
Disables the peaking filter in luma s-video channel
Enables the peaking filter in luma s-video channel
Chroma Filter Adjust
Low bandwidth
Medium bandwidth
Med-high bandwidth
High bandwidth
Luma S-Video Filter Adjust
6
CVBW
R/W
0
5
CBW1
R/W
0
4
CBW0
R/W
0
3
YPEAK
R/W
0
2
YSV1
R/W
0
Symbol: VBW
Address: 03H
Bits: 8
1
YSV0
R/W
0
CH7008A
0
YCV
R/W
0
31
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