CH7008A-V ETC [List of Unclassifed Manufacturers], CH7008A-V Datasheet - Page 7

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CH7008A-V

Manufacturer Part Number
CH7008A-V
Description
Digital PC to TV Encoder Features
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
Input Data Formats
The XCLK and XCLK* signals are used to latch data from the graphics chip. Data can be latched coincident with
the rising edge of XCLK, falling edge of XCLK, or both edges, depending upon register settings of XCM and MCP.
The input data format is shown in Figure 4. The Pixel Data bus represents an 8 or 12-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. In IDF settings of 4, 5, 7, 8 and 9, the input data rate is 2X
pixel clock, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel, encoded as shown in the
tables below. When the input is YCrCb, the color-difference data will be transmitted at half the data rate of the lumi-
nance data, with the sequence being set as Cb0, Y0, Cr0, Y1 where Cb0,Y0,Cr0 refers to co-sited luminance and
color-difference samples — and the following Y1 byte refers to the next luminance sample, per CCIR656 standards.
However, the clock frequency is dependent upon the current mode, not 27MHz, as specified in CCIR656
CHRONTEL
Table 3. RGB 8-bit Multiplexed Mode
201-0000-027 Rev 2.2, 9/30/99
HS
DS / BCO
XCLK
XCLK*
XCLK
XCLK*
D[11:0]
Pixel#
Bus Data
Format
IDF#
(XCM=01)
(XCM=00)
(XCM=01)
(XCM=00)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
When DSEN=1(bit 4 of register 1Ch), SAV should be set to 11d.
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
Figure 4: Non-multiplexed Data Transfers
(DSEN=0)
P0b
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[5]
G0[4]
G0[3]
SAV
RGB 5-6-5
7
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[5]
G1[4]
G1[3]
P0a
P0a
G0[2]
G0[1]
G0[0]
B0[4]
B0[3]
B0[2]
B0[1]
B0[0]
P0b
P1a
P0b
x
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[4]
G0[3]
RGB 5-5-5
P1b
8
P1a
G1[2]
G1[1]
G1[0]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P2a
CH7008A
.
P1b
x
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[4]
G1[3]
P2b
7

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