QL2009-0PB256C ETC [List of Unclassifed Manufacturers], QL2009-0PB256C Datasheet - Page 11

• Manufacturer Part Number: QL2009-0PB256C
• Description: 3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Clock Cells
I/O Cells
Notes:
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of
[11] The following loads are used for tPXZ:
Symbol
Symbol
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
tACK
tGCKP
tGCKB
Symbol
tI/O
tISU
tIH
tlOCLK
tlORST
tlESU
tlEH
QL2009
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Input Delay (bidirectional pad)
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register clock Enable Set-Up Time
Input Register Clock Enable Hold Time
Parameter
Parameter
Parameter
3-45
1K
2.2
1.2
1.5
1
2.6
2.8
2.1
2.6
2.9
3.3
30
1.8
4.8
0.0
0.8
0.7
4.1
0.0
1
Output Load Capacitance (pF)
2.2
1.2
1.6
Loads per Half Column [10]
2
Propagation Delays (ns)
Propagation Delays (ns)
Propagation Delays (ns)
2.1
4.8
1.1
1.0
4.1
0.0
0.0
2
3.0
3.3
2.6
3.3
50
tPHZ
5 pF
2.3
1.2
1.6
3
Fanout [8]
2.4
4.8
0.0
1.4
1.3
4.1
0.0
3
3.6
3.9
4.1
2.4
1.2
1.7
3.1
75
4
2.7
1.7
1.6
4.1
4.8
0.0
0.0
4
2.5
1.2
1.8
8
100
4.1
4.5
3.7
4.9
1K
3.9
4.8
0.0
2.9
2.8
4.1
0.0
8
2.6
1.2
1.9
10
150
5.2
5.7
4.8
6.5
tPLZ
5 pF
4.6
3.6
4.8
0.0
3.5
4.1
0.0
10
1.2
2.0
13
3