DM9161BIEP DAVICOM [Davicom Semiconductor, Inc.], DM9161BIEP Datasheet - Page 32

• Manufacturer Part Number: DM9161BIEP
• Description: Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

8.12 (Specified config) Register – 20
8.13 DAVICOM Specified Interrupt Register – 21
Preliminary
Version: DM9161BI-12-DS-P01
July 16, 2008
20.15
20.14
20.13
20.12
20.11
20.10
21.15
20.9
20.8
20.7
20.6
20.5
20.4
20.3
20.2
20.1
20.0
Bit
Bit
FORCE_TXSD
AutoNeg_dpbk
Mdix_fix Value
PREAMBLEX
TX10M_PWR
NWAY_PWR
INTR PEND
Mdix_do wn
MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value
Bit Name
TSTSEL3
Reserved
PD_value
Bit Name
RMII_Ver
MonSel1
MonSel0
TSTSE1
TSTSE2
Default
Default
0, RW
0, RO
0, RO
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Vendor test select control
Vendor test select control
Force Signal Detect
1: force SD signal OK in 100M
0: normal SD signal.
Vendor test select control
Preamble Saving Control
1: 10M TX preamble bit count is normal.
0: when bit 10 is set, the 10M TX preamble count is reduced.
10M TX Power Saving Control
1: enable 10M TX power saving
0: disable 10M TX power saving
N-Way Power Saving Control
1: disable N-Way power saving
0: enable N-Way power saving
Reserved
Read as 0, ignore on write
1: MDIX mode
0: MDI mode
Auto-negotiation Loopback
1: test internal digital auto-negotiation Loopback
0: normal.
MDIX_CNTL force value:
When MDIX_DOWN = 1, MDIX_CNTL value depend on the register
value.
MDIX Down
Manual force MDI/MDIX.
0: Enable HP Auto-MDIX
1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5
Vendor monitor select
Vendor monitor select
RMII version
0: support RMII 1.2
1: support RMII 1.0
Power down control value
Decision the value of each field Register 19.
1: power down
0: normal
Interrupt Pending
Indicates that the interrupt is pending and is cleared by the current
read. This bit shows the same result as bit 0. (INTR Status)
When bit 11 of register 29 is set, 10-bit preamble bit is reduced;
otherwise 20-bit preamble bits is reduced.
Description
Description
DM9161BI
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