GL850G-MNGXX GENESYS [GENESYS LOGIC], GL850G-MNGXX Datasheet

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GL850G-MNGXX

Manufacturer Part Number
GL850G-MNGXX
Description
USB 2.0 HUB Controller
Manufacturer
GENESYS [GENESYS LOGIC]
Datasheet

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Part Number:
GL850G-MNGXX
Manufacturer:
ALLEGRO
Quantity:
252
Genesys Logic, Inc.
GL850G
USB 2.0
HUB Controller
Datasheet
Revision 1.04
Aug. 08, 2007

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GL850G-MNGXX Summary of contents

Page 1

... Genesys Logic, Inc. GL850G USB 2.0 HUB Controller Datasheet Revision 1.04 Aug. 08, 2007 ...

Page 2

... All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 2 ...

Page 3

... Date 1.00 05/10/2006 First formal release 1.01 08/30/2006 Updated DC Supply Current, Table6.6, P.23 1.02 11/03/2006 Modify 93C46 Configuration, Table 5.1, P.19 1.03 01/17/2007 Modify Table 6.1-Maximum Ratings, P.21 1.04 08/08/2007 Modify Table 6.6-DC Supply Current, P.23 ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Revision History Description Page 3 ...

Page 4

... ONFIGURATION AND CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 21 6 AXIMUM ATINGS 6 PERATING ANGES 6 HARACTERISTICS 6 OWER ONSUMPTION CHAPTER 7 PACKAGE DIMENSION..................................................... 24 CHAPTER 8 ORDERING INFORMATION ............................................ 25 ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller TABLE OF CONTENTS ................................................................................... 10 I/O S ....................................................... 16 ETTINGS ................................................................................. 21 ................................................................................ 21 ............................................................................ 21 ............................................................................ 23 Page 4 ...

Page 5

... F 3.1- - - - GL850G 48 P IGURE F 4.1 – GL850G B IGURE F 5.1 – O IGURE PERATING IN F 5.2 – O IGURE PERATING IN F 5.3 – P IGURE OWER ON SEQUENCE OF F 5.4 – T IGURE IMING OF F 5.5 – I IGURE NDIVIDUAL F 5.6 – SELF/BUS P IGURE F 5.7 – LED C IGURE ONNECTION F 5.8 – S IGURE CHEMATICS F 7.1 – GL850G 48 P IGURE © ...

Page 6

... T 3.1- - - - GL850G 48 P ABLE T 3 ABLE IN ESCRIPTIONS T 5.1 – 93C46 C ABLE ONFIGURATION T 6.1 – M ABLE AXIMUM T 6.2 – O ABLE PERATING T 6.3 – ABLE HARACTERISTICS T 6.4 – ABLE HARACTERISTICS OF T 6.5 – ABLE HARACTERISTICS OF T 6.6 – ABLE UPPLY T 8.1 – O ABLE RDERING © ...

Page 7

... EEPROM (Ref. to Chapter 5). Each downstream port of GL850G supports two-color (green/amber) status LEDs to indicate normal/abnormal status. GL850G also support both Individual and Gang modes (4 ports as a group) for power management. The GL850G is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs ...

Page 8

... Full function in 48-pin LQFP package • Applications: − Stand-alone USB hub − PC motherboard USB hub, Docking of notebook LCD monitor hub − Any compound device to support USB HUB function − ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 8 ...

Page 9

... CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts Figure 3.1 ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller GL850G - - - - G L850G 48 Pin LQFP Pinout Diagram Page 9 ...

Page 10

... DM4,DP4 21,22 RREF 11 Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL850G Design Guideline. ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller - - - - Table 3.1 G L850G 48 Pin List 13 AGND P 25 DVDD ...

Page 11

... Individual/gang mode is strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. B When GL850G is suspended, this pin will output low. *For detailed explanation, please see Chapter 5 Gang input:1, output: 0@normal, 1@suspend ...

Page 12

... DVDD 38, V33 48 Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL850G Design Guideline. Notation: Type O Output I Input I_5V 5V tolerant input B Bi-directional ...

Page 13

... USPORT Transceiver UTMI REPEATER DSPORT1 Logic DSPORT Transceiver D- LED/ D+ OVCUR/ PWRENB Figure 4.1 – GL850G Block Diagram (single TT) ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller 12MHz PLL FRTIMER x40, x10 USPORT SIE Logic TT (Transaction Translator) REPEATER / TT Routing Logic ...

Page 14

... The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0. 5.1.4 µ the micro-processor unit of GL850G 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, C can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub ...

Page 15

... TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL850G adopts the single TT architecture to provide the most cost effective solution. Single TT shares the same buffer control module for each downstream port. GL852 adopts multiple TT architecture to provide the most performance effective solution ...

Page 16

... Configuration and I/O Settings 5.2.1 RESET# Setting GL850G integrates in the pull-up 15K resister of the upstream port. When RESET# is enabled, the internal 15K pull-up resister will be disconnected to the 3.3V power. To meet the requirement (p.141) of the USB 2.0 specification, pull-up resister should be disconnected while lacking of USB cable power (Vbus). © ...

Page 17

... GL850G internally contains a power on reset circuit. The power on sequence is depicted in the next picture. To fully control the reset process of GL850G, we suggest the reset time applied in the external reset circuit should longer than that of the internal reset circuit. Internal reset External reset Figure 5.3 – Power on sequence of GL850G 5 ...

Page 18

... Figure 5.5 – Individual/GANG Mode Setting 5.2.3 SELF/BUS Power Setting GL850G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850G can be configured as a bus-power or a self-power hub. 1: Power Self 0: Power Bus © ...

Page 19

... GL850G is globally suspended, GL850G will turn off the LED to save power. AMBER/GREEN Inside GL850G 5.2.5 EEPROM Setting GL850G replies to host commands by the default settings in the internal ROM. GL850G also offers the ability to reply to the host according to the settings in the external EEPROM(93C46). The following table shows the configuration of 93C46. Unit: Byte ...

Page 20

... EE_DO Figure 5.8 – Schematics Between GL850G and 93C46 GL850G firstly verifies the check sum after power on reset. If the check sum is correct, GL850G will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists. ...

Page 21

... HIGH level output voltage when Pad internal pull down resister DN R Pad internal pull up resister UP ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 6.1 – Maximum Ratings Parameter Table 6.2 – Operating Ranges Parameter Parameter =8mA OL =8mA OH Min ...

Page 22

... DP/DM HS static output LOW Transceiver capacitance IN I Hi-Z state data line leakage LO Z Driver output resistance for USB 2.0 HS DRV ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Parameter of 1. 15K to GND ) L Parameter of 1. Min. Typ. Max. Unit ...

Page 23

... Power Consumption Symbol Active ports I SUSP Active *1: F: Full-Speed, H: High-Speed ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 6.6 – DC Supply Current Condition Host Device Suspend * ...

Page 24

... CHAPTER 7 PACKAGE DIMENSION Figure 7.1 – GL850G 48 Pin LQFP Package ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller GL850G AAAAAAAGAA YWWXXXXXXXX Page 24 ...

Page 25

... CHAPTER 8 ORDERING INFORMATION Part Number GL850G-MNNXX 48-pin LQFP GL850G-MNGXX 48-pin LQFP ©2000-2007 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 8.1 – Ordering Information Package Normal/Green Normal Package Green Package Version Status XX XX Page 25 ...

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