LC51024MV-75F484I Lattice Semiconductor, LC51024MV-75F484I Datasheet - Page 12

• Manufacturer Part Number: LC51024MV-75F484I
• Description: CPLD ispXPLD? 5000MV Family 300K Gates 1024 Macro Cells 200MHz Industrial EECMOS Technology 3.3V 484-Pin FPBGA
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
Single-Port SRAM Mode
In Single-Port SRAM Mode the multi-function array is configured as a single-port SRAM. In this mode one ports
accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 11 shows
the block diagram of the single-port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Reset is asynchronous. All signals share a common clock, clock
enable, and reset. Table 7 shows the possible sources for the clock, clock enable and reset signals.
Figure 11. Single-Port SRAM Block Diagram
Table 7. Register Clock, Clock Enable, and Reset in Single-Port SRAM Mode
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Register
Clock
Clock Enable
Reset
RESET
68 Inputs
CLK0
CLK1
CLK2
CLK3
Routing
from
Input
Write/Read
Clk Enable
Reset
Read/Write Address
(AD[0-8:13])
Write Data
(DI[0-0,1,3,7,15,31])
Clock
Chip Select
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
CEN or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired.
(RST)
(CLK)
(CEN)
(WR)
(CS0,1)
12
16,384-Bit
‘
‘
SRAM
Array
ispXPLD 5000MX Family Data Sheet
Source
Read Data
(DO[0-0,31])