LC51024MV-75F484I Lattice Semiconductor, LC51024MV-75F484I Datasheet - Page 18

• Manufacturer Part Number: LC51024MV-75F484I
• Description: CPLD ispXPLD? 5000MV Family 300K Gates 1024 Macro Cells 200MHz Industrial EECMOS Technology 3.3V 484-Pin FPBGA
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
Figure 17. I/O Cell
Table 10. Shared PTOE Segments
sysIO Standards
Each I/O within a bank is individually configurable based on the V
require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for
V
TN1000, sysIO Usage Guidelines for Lattice Devices, available at www.latticesemi.com.
Table 11. Number of I/Os per Bank
CCO,
V
REF
and V
TT.
For more information on the sysIO capability, please refer to Lattice technical note number
Data Output from
Alternate Macrocells
Data Output from
Primary Macrocell
Shared PTOE 0
Shared PTOE 1
Shared PTOE 2
Shared PTOE 3
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
To Alternate
Macrocell
To Primary
Macrocell
GOE0
GOE1
PTOE
Device
TOE
Device
Output Sharing
Array (OSA)
To Adjacent I/O Pad
Data Input to Routing
Delay Element
Maximum Number of I/Os per Bank (n)
MFBs Associated With Segments
(Y, Z, AA, AB) (AC, AD, AE, AF)
18
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(Q, R, S, T) (U, V, W, Z)
(A, B, C, D) (E, F, G, H)
(Q, R, S, T) (U, V, W, Z)
(I, J, K, L) (M, N, O, P)
(I, J, K, L) (M, N, O, P)
(I, J, K, L) (M, N, O, P)
Output Buffer
(V
for Open Drain
Outputs)
V
Input Buff
CCO
REF
Differential
Output Buffer
V
Other I/Os
CCO
in Bank
Independent
Dependent
36
68
96
96
Differential
I/O Buffer
(V
CCO
ispXPLD 5000MX Family Data Sheet
to All
REF
er
CMOS/TTL
Input Buffer
Independent)
and V
To Adjacent
I/O Pad
+
–
+
–
REF
this Bank
V
GND
CCO
V
other I/Os in Bank
REF
settings. Some standards also
for
to All
Pad
I/O